GitHub / nxbyte / Verilog-Projects
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nxbyte%2FVerilog-Projects
PURL: pkg:github/nxbyte/Verilog-Projects
Stars: 91
Forks: 21
Open issues: 3
License: mit
Language: Verilog
Size: 2.23 MB
Dependencies parsed at: Pending
Created at: about 9 years ago
Updated at: over 1 year ago
Pushed at: over 5 years ago
Last synced at: over 1 year ago
Topics: adder, comparator, decoder, encoder, full-adder, half-adder, look-ahead-adder, multiplexer, priority, ripple-adder, simulator, system-verilog, testbenches, traffic-light-controller, verilog, xilinx, xilinx-vivado