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GitHub / nxbyte / Verilog-Projects
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/nxbyte%2FVerilog-Projects
Stars: 91
Forks: 21
Open Issues: 3
License: mit
Language: Verilog
Repo Size: 2.23 MB
Dependencies:
0
Created: about 8 years ago
Updated: 8 months ago
Last pushed: over 4 years ago
Last synced: 8 months ago
Topics: adder, comparator, decoder, encoder, full-adder, half-adder, look-ahead-adder, multiplexer, priority, ripple-adder, simulator, system-verilog, testbenches, traffic-light-controller, verilog, xilinx, xilinx-vivado
Files
No dependencies found