GitHub topics: nexys4ddr
brown9804/NexysDDR4-RISC-V_picorv32
Using VIVADO, Nexys DDR 4 board with RISC-V PicoRV32 CPU
Language: Verilog - Size: 85 MB - Last synced at: 7 days ago - Pushed at: 8 days ago - Stars: 2 - Forks: 3
LuisMLopez-dev/Double-Dabble-Algorithm
This is a VHDL code for converting a binary number to a BCD (binary-coded decimal) number using the Double Dabble Algorithm.
Language: VHDL - Size: 7.81 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
TahirZia-1/UART-Transmitter-and-Receiver
A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.
Language: SystemVerilog - Size: 231 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
TahirZia-1/Digital-Clock-Verilog
This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.
Language: Tcl - Size: 166 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
ishifr/fpga_prototyping_codes
FPGA prototyping by Verilog examples kitobini o'qish davomida yozilgan kodlar to'plami. Nexys4DDR(Artix-7) dev board'dan foydalanilgan. A collection of code written while reading the book FPGA prototyping by Verilog examples. Nexys4DDR(Artix-7) dev board is used
Language: Tcl - Size: 0 Bytes - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0
shreegw/FPGA-Thermostat-Controller
A Thermostat controller designed using the temperature sensor on the Nexys-4 module
Language: Verilog - Size: 104 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0
shinesunnysom/Biofeedback-Game-System
CECS 490A/490B Course; Senior Project Design
Language: Verilog - Size: 742 KB - Last synced at: 2 months ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 0
luminoso/cr-countones
Xilinx Vivado demo project with design, IP, SDK interaction, VGA, finite state machine and outputs
Language: VHDL - Size: 25.6 MB - Last synced at: 7 months ago - Pushed at: almost 8 years ago - Stars: 7 - Forks: 1
syedahmedullah14/AI-on-air
A cutting-edge AI SaaS platform that enables users to create, discover, and enjoy podcasts with advanced features like text-to-audio conversion with multi-voice AI, podcast thumbnail image generation, and seamless playback. The platform is built using Next.js, TypeScript, Convex, OpenAI, Stripe, Clerk, ShadCN, and Tailwind CSS.
Language: TypeScript - Size: 10.8 MB - Last synced at: 2 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0
yidiwang21/Nexys-4-Projects
Mini projects based on Xilinx Nexys 4 DDR
Language: VHDL - Size: 1.02 MB - Last synced at: 7 months ago - Pushed at: over 7 years ago - Stars: 7 - Forks: 2
iBug/Nexys4-DDR-stopwatch 📦
A stopwatch on Digilent Nexys4 DDR written in Verilog
Language: VHDL - Size: 2.47 MB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0
7enTropy7/Artix_7
My experiments with Nexys4 DDR Artix-7 FPGA Board
Language: Verilog - Size: 31.3 KB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 3
Elon-Wang/Breakout
Using the FPGA board Nexys Artix-7 to design a breakout game with vhdl language.
Language: VHDL - Size: 29.7 MB - Last synced at: about 1 year ago - Pushed at: about 6 years ago - Stars: 2 - Forks: 0
GraceSevillano/RTIC-project-Antoine-s-army
This project not only provides hands-on experience with VHDL but also offers insight into the fundamental concepts of CPU architecture and design. It bridges the gap between theoretical knowledge and practical application, using the Nexys4 DDR board as a testbed
Language: VHDL - Size: 12.3 MB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
Louis-GUENEGO/NEXYS4ddr_microphone
An audio project with the NEXYS 4 ddr
Language: VHDL - Size: 3.85 MB - Last synced at: about 1 month ago - Pushed at: about 3 years ago - Stars: 6 - Forks: 2
santifs/simon-game-vhdl
VHDL game that displays incremental random sequences on an LED Matrix by creating a finite state machine and implementing RAM and ROM models.
Language: VHDL - Size: 7.94 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 1
santifs/ultrasonic-sensor
Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.
Language: VHDL - Size: 6.83 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 8 - Forks: 2
davismariotti/HelicopterGame
A helicopter game written for the Nexys 4 DDR Board in VHDL
Language: VHDL - Size: 12 MB - Last synced at: almost 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 3
nickschiffer/fsm_calculator
A finite state machine controlled calculator written using Verilog in Xilinx Vivado targeting the Nexys 4 DDR FPGA Board
Language: Verilog - Size: 8.2 MB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 4 - Forks: 2
shinde-shantanu/FPGA_TDC
Time to Digital Converter on an FPGA
Language: VHDL - Size: 52.6 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 2
edw4rdyao/sdcard_digital_recognition
💾FPGA based SD card reads and displays pictures🎞 and performs digital recognition experiments.
Language: Verilog - Size: 2.55 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 5 - Forks: 1
nickschiffer/parallel_unsigned_integer_multiplier
Xilinx Vivado Project
Language: Verilog - Size: 2.74 MB - Last synced at: about 2 years ago - Pushed at: about 7 years ago - Stars: 6 - Forks: 1
zhongyuchen/mips-32bit
Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board
Language: Verilog - Size: 160 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 6 - Forks: 5
jideoyelayo1/PongGameVerilog
A Pong Game made in Verilog
Language: SystemVerilog - Size: 4.73 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
lild4d4/usm_microcontroller_v1
Undergraduate level RISC-V microcontroller
Language: SystemVerilog - Size: 201 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0
Juanx65/Aguilera_Mardones_T4_3_1_IPD432
Tarea 4 Parte 3.1 IPD432 - Procesador de vectores para Nexys4 DDR
Language: VHDL - Size: 87 MB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0
nickschiffer/cla_adder_7seg
4bit_CLA_Adder_7seg in Xilinx Vivado Verilog
Language: HTML - Size: 601 KB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0
cesar-avalos3/ROM_Controller
Nexys 4 DDR - Rom Controller
Language: VHDL - Size: 20.5 KB - Last synced at: about 2 years ago - Pushed at: about 7 years ago - Stars: 2 - Forks: 0
cmfcmf/vhdl-demo
A simple text editor written in VHDL for the Nexys 4 DDR Evaluation board.
Language: VHDL - Size: 1.97 MB - Last synced at: 8 months ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0
austinbhale/MIPS-Stacker
Stacker Arcade Game in MIPS Assembly Language
Language: VHDL - Size: 94.7 KB - Last synced at: 4 months ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0
zhongyuchen/dlcd-lab
Digital Logical and Component Design Lab (COMP130003.01), 2017/2018, 1
Language: Verilog - Size: 28.6 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0
ken-diep/Digital-Systems-Design-Game
A platformer game coded in Verilog for the Nexys 4 DDR Artix-7 FPGA.
Language: Verilog - Size: 6.84 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0
