maxboro/emulated-uart-connection

Device connection and data transmission via UART - simple example

Language: C - Size: 29.3 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

TahirZia-1/UART-Transmitter-and-Receiver

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.

Language: SystemVerilog - Size: 231 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

pConst/basic_verilog

Must-have verilog systemverilog modules

Language: Verilog - Size: 54.2 MB - Last synced at: 7 months ago - Pushed at: 10 months ago - Stars: 1,627 - Forks: 376

oskarwires/uart2

SystemVerilog UART transciever

Language: SystemVerilog - Size: 87.9 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

dipakgmx/ATMega_Serial

Serial communacation (USART) on the ATMega 2560 using C++ classes

Language: C++ - Size: 22.5 KB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 6 - Forks: 1

onegentig/VUT-FIT-INC2022-projekt 📦

Projekt (UART přijímací část) z předmětu Návrh číslicových systémů (INC), druhý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2021/2022

Language: VHDL - Size: 255 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

TheLeopardsH/UART

Universal Asynchronous Receiver Transmitter

Language: Verilog - Size: 5.86 KB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 0

manish5897/esp32_uart

UART receive task

Language: C++ - Size: 8.79 KB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 3 - Forks: 0

kishanpatelec/UART-for-bluetooth-module

Language: Verilog - Size: 16.6 KB - Last synced at: over 1 year ago - Pushed at: about 6 years ago - Stars: 3 - Forks: 0

AhsanAliUet/uart-application-in-real-time-simulation-emulation-on-fpga

If we run out of input pins on FPGA, we can instantiate receiver of uart in DUT (design under test). Receiver will receive data from PC serially and convert this serial data to parallel data and give it to DUT to use it without hesitation of shortage of input pins.

Language: HTML - Size: 1.2 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

MiguelNarv/UART-Receiver-VHDL

Low resource UART receiver for FPGA.

Language: VHDL - Size: 667 KB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

windfallw/ESP32-Air-Monitor 📦

This is an ESP32 project for receiving json from another device by uart and send it to the server. Also provide web service for management.

Language: Python - Size: 1.8 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0