GitHub topics: processor-architecture
leticia-pontes/vhdl
Códigos e imagens de simulação de circuitos lógicos desenvolvidos em aula
Language: VHDL - Size: 544 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 0 - Forks: 0
Mariotti94/WebRISC-V
WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
Language: PHP - Size: 2.08 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 147 - Forks: 10
sstsimulator/sst-elements
SST Architectural Simulation Components and Libraries
Language: C++ - Size: 167 MB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 96 - Forks: 129
jmuehlig/perf-cpp
Lightweight recording and sampling of performance counters for specific code segments directly from your C++ application.
Language: C++ - Size: 756 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 65 - Forks: 8
jbush001/NyuziProcessor
GPGPU microprocessor architecture
Language: C - Size: 31.4 MB - Last synced at: 15 days ago - Pushed at: 7 months ago - Stars: 2,082 - Forks: 360
mikeroyal/RISC-V-Guide
RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
Language: Assembly - Size: 1.07 MB - Last synced at: 19 days ago - Pushed at: over 1 year ago - Stars: 576 - Forks: 48
mortbopet/Ripes
A graphical processor simulator and assembly editor for the RISC-V ISA
Language: C++ - Size: 43.8 MB - Last synced at: 23 days ago - Pushed at: about 1 month ago - Stars: 2,872 - Forks: 295
intel/pcm
Intel® Performance Counter Monitor (Intel® PCM)
Language: C++ - Size: 6.01 MB - Last synced at: 23 days ago - Pushed at: about 1 month ago - Stars: 3,002 - Forks: 492
hlorenzi/customasm
💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/
Language: Rust - Size: 5.24 MB - Last synced at: 23 days ago - Pushed at: about 1 month ago - Stars: 943 - Forks: 64
Leandro-rdz/Compilateur-MICroprocesseur
Une implémentation très simpliste d'un compilateur de code C et d'un microprocesseur associé
Language: VHDL - Size: 1.27 MB - Last synced at: 24 days ago - Pushed at: 25 days ago - Stars: 0 - Forks: 0
OpenSourceSilicon/32-bit-MIPS-CPU
An implementation of a 32-bit DLX(a derivative of MIPS) architecture based RISC processor in verilog
Language: Verilog - Size: 18.6 KB - Last synced at: 27 days ago - Pushed at: 27 days ago - Stars: 0 - Forks: 0
VadanShah/3-Stage-ALU-Pipeline-Processor
🚀 Verilog-based 3-stage pipelined ALU processor supporting ADD, SUB, AND, OR, MUL (Booth’s), and DIV (Restoring) operations.
Size: 0 Bytes - Last synced at: 29 days ago - Pushed at: 29 days ago - Stars: 0 - Forks: 0
jayasuriyanicol/Undergraduate-Course-Electronic-Calculators
Welcome to the Digital Computers Course repository! 💻 This repository serves as a central hub for materials, exercises, and projects developed throughout the course, which explores the principles of computer architecture, digital circuit design, and low-level programming.
Language: Assembly - Size: 90.8 KB - Last synced at: 29 days ago - Pushed at: 29 days ago - Stars: 0 - Forks: 0
icarogabryel/flote
Flote is a HDL and Python framework for simulation. Designed to be friendly, simple, and productive. Easy to use and learn.
Language: Python - Size: 349 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 1 - Forks: 0
caleb531/cache-simulator
A processor cache simulator for the MIPS architecture
Language: Python - Size: 141 KB - Last synced at: 29 days ago - Pushed at: 2 months ago - Stars: 39 - Forks: 18
SKpro-glitch/RISCV-Processor-ASIC
This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.
Language: Verilog - Size: 138 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0
VB-123/MINI-RISC-Pipeline
A 16-bit RISC Processor, with a four stage pipeline
Language: Verilog - Size: 327 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0
scopeInfinity/QLifeProcessor
General-purpose processor with a 16-bit address & 32-bit data bus
Language: Python - Size: 175 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
ubaidrmn/RISC-V-assembly
RISC-V assembly code I wrote as part of my COAL course at UIT University.
Size: 14.6 KB - Last synced at: 2 months ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0
luk3Sky/Building-A-Processor---Project
Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic
Language: Verilog - Size: 880 KB - Last synced at: 3 months ago - Pushed at: over 6 years ago - Stars: 8 - Forks: 1
Zachary-Pearce/Pomegranate
An open source portable and scalable soft-core processor written in VHDL.
Language: VHDL - Size: 2.33 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 1 - Forks: 0
GeekAlexis/superscalar-mips
A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines
Language: Verilog - Size: 47.1 MB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 10 - Forks: 3
astrogeekdk/RISC-V-Basic-SIMD
A basic implemention of 8 lane vector SIMD in RISC-V 5 Stage Pipeline, written in Chisel and Scala.
Language: Scala - Size: 12.7 KB - Last synced at: 3 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0
helcsnewsxd/famaf-computer_science-computer_architecture-lab1 📦
Laboratorio 1 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
Language: SystemVerilog - Size: 2.55 MB - Last synced at: 3 months ago - Pushed at: 11 months ago - Stars: 1 - Forks: 0
helcsnewsxd/famaf-computer_science-computer_architecture-lab2 📦
Laboratorio 2 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
Language: Assembly - Size: 1.85 MB - Last synced at: 3 months ago - Pushed at: 11 months ago - Stars: 2 - Forks: 0
helcsnewsxd/famaf-computer_science-computer_architecture 📦
Laboratorios, prácticos y teóricos de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
Language: SystemVerilog - Size: 6.83 MB - Last synced at: 3 months ago - Pushed at: 11 months ago - Stars: 2 - Forks: 0
meiniKi/RV32I_SC_Logisim
A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.
Language: Verilog - Size: 707 KB - Last synced at: 3 months ago - Pushed at: about 2 years ago - Stars: 5 - Forks: 0
physical-computation/sunflower-embedded-system-emulator
Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architecture modeling of Hitachi SH (j-core), RISC-V, and more.
Language: C - Size: 305 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 25 - Forks: 218
guntas-13/mips-processor-basys3
Full FPGA Implementation of 32-bit FSM-based Multi-State MIPS Processor
Language: Verilog - Size: 92.7 MB - Last synced at: 3 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 1
tscheipel/HaDes-V
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.
Language: SystemVerilog - Size: 432 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 35 - Forks: 2
elvircrn/MIC-1
A microprocessor implemented in VHDL
Language: C++ - Size: 5.06 MB - Last synced at: 3 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 1
RPTU-EIS/ADSProject
This repository contains the basic files for the class project of the course "Architecture of Digital Systems I"
Language: Scala - Size: 1.24 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 3 - Forks: 16
dzen-g-neere/8-bit-processor
8-bit Processor emulator designed and impemented using Java SE
Language: Java - Size: 47.9 KB - Last synced at: 3 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0
cwielder/coldcpu
Custom processor architecture, assembly language, and toolchain.
Language: C++ - Size: 830 KB - Last synced at: 3 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0
aitesam961/16-Bit-RISC-Core-Processor
A RISC custom-ISA, 16-Bit Processor
Language: Verilog - Size: 22.2 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 8 - Forks: 1
jotavare/x86-assembly-nasm
Explored x86 assembly programming using NASM, dived into low-level coding and discovered the inner workings of computer hardware and software.
Language: Assembly - Size: 58.6 KB - Last synced at: 4 months ago - Pushed at: 12 months ago - Stars: 1 - Forks: 0
Abd-El-Rahman-Sabry/processing-unit-with-uart
This project implements a UART-controlled processing unit with dual clock domains for UART communication and datapath operations. A state machine decodes serial commands to control the datapath, enabling ALU operations, register file access, and data transmission. It's designed for embedded systems and educational purposes.
Language: Verilog - Size: 1.79 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0
prantoamt/16bit_processor_design
Size: 292 KB - Last synced at: about 1 month ago - Pushed at: over 6 years ago - Stars: 12 - Forks: 6
VimalanKM/Chip-Multi-Processors-Memory-System-Advanced-Cache-DRAM-Design-for-Multicore-Processors
This is a simulation of multicore processor where a memory system with L1 cache, L2 cache and DRAM has been implemented.
Language: C++ - Size: 21.5 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0
VimalanKM/Superscalar-Pipeline-and-Branch-Prediction-Simulator
Implements a superscalar pipeline with data dependency tracking, forwarding, and branch prediction to evaluate performance and optimize CPU execution.
Language: C++ - Size: 15.2 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0
z1skgr/VHDL-processor-CHARIS
Architecture of processor designed in vhdl
Language: VHDL - Size: 16.4 MB - Last synced at: 3 months ago - Pushed at: 6 months ago - Stars: 2 - Forks: 0
Abdulrahman-Mostafa10/Computer-Architecture-Labs
A repo for my academic course for the computer architecture to mark up my way till we implement our RISC processor 🚀🚀
Language: VHDL - Size: 1.04 MB - Last synced at: 4 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 1
tay-assis/SimulatorR8
Simulador do Processador R8 com a implementação de uma unidade externa (co-processador) para processamento matricial 4x4.
Language: VHDL - Size: 21.5 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0
bansal-yash/COL216-Computer-Architecture
Course assignments of COL216:- Computer Architecture course at IIT Delhi under Professor Kolin Paul
Language: VHDL - Size: 37 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0
worthant/OPD
:computer: This course is about computer science basics.
Language: Assembly - Size: 9.84 MB - Last synced at: 2 months ago - Pushed at: almost 2 years ago - Stars: 7 - Forks: 0
mtumilowicz/java17-mesi-false-sharing-processor-optimisations-workshop
Introduction to cache coherence: false sharing, MESI protocol and vectorization
Language: Java - Size: 428 KB - Last synced at: 4 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0
KaririCode-Framework/kariricode-processor-pipeline
A flexible and extensible processor pipeline component for the KaririCode framework. Enables the creation of modular, configurable processing chains for data transformation, validation, and sanitization tasks
Language: PHP - Size: 195 KB - Last synced at: 16 days ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0
alirezakay/RISC-CPU
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
Language: VHDL - Size: 2.52 MB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 27 - Forks: 5
icarogabryel/sea-iv
SEA-IV is a simple assembler for the MOOn-IV architecture. It is written in Python 3 and is a command-line tool.
Language: Python - Size: 151 KB - Last synced at: 3 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
Mograsim-Team/Mograsim
Modular Graphical Simulator for Teaching Microprogramming
Language: Java - Size: 4.5 MB - Last synced at: 5 days ago - Pushed at: 6 months ago - Stars: 12 - Forks: 1
RiscJ-blockits/riscj-computer-mod
Language: Java - Size: 3.19 MB - Last synced at: about 2 months ago - Pushed at: about 1 year ago - Stars: 4 - Forks: 0
sdasgup3/parallel-processor-design
Super scalar Processor design
Language: Verilog - Size: 137 KB - Last synced at: 2 months ago - Pushed at: almost 11 years ago - Stars: 21 - Forks: 3
thenamangoyal/RISC-Simulator
A C++ pipeline based simulator of RSIC architecture.
Language: C++ - Size: 431 KB - Last synced at: 11 months ago - Pushed at: almost 5 years ago - Stars: 7 - Forks: 1
kara-abdelaziz/SEP-CPU
SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU
Language: Assembly - Size: 201 KB - Last synced at: 11 months ago - Pushed at: almost 4 years ago - Stars: 5 - Forks: 1
SSK015/System-Interview-notes
Interview-notes on aspects of Computer Systems.
Size: 1.33 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0
PhongDiii/Simulation-in-System-Engineer
Push files I did in Simulation field as well as some good model that promote my interests.
Size: 88.3 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 3 - Forks: 0
fguzman82/upb_natalius_soc
8 bit RISC Processor for SKY 130nm process
Language: Verilog - Size: 56.3 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 1 - Forks: 0
tilk/sextium-asm
Tools for the Sextium III architecture
Language: Haskell - Size: 18.6 KB - Last synced at: about 1 year ago - Pushed at: over 8 years ago - Stars: 0 - Forks: 0
tilk/sextium-iii-verilog
Sextium® III processor implemented in Verilog
Language: Verilog - Size: 226 KB - Last synced at: about 1 year ago - Pushed at: almost 7 years ago - Stars: 3 - Forks: 0
whatever125/OPD
Лабораторные работы и учебные материалы по курсу «Основы Профессиональной Деятельности», ИТМО ИВТ 1 курс 2022-2023
Language: Shell - Size: 84.6 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0
NSU-ACM-SC/16bit_processor_design
Size: 292 KB - Last synced at: about 1 month ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 0
GodTamIt/tomasulo-simulation
A simulation of the Tomasulo algorithm, a hardware algorithm for out-of-order scheduling and execution of computer instructions, written in C++.
Language: C++ - Size: 364 KB - Last synced at: about 2 months ago - Pushed at: about 8 years ago - Stars: 14 - Forks: 0
shyamal-anadkat/WISC-SP13
CS 552 term project : functional design of a microprocessor called the WISC-SP13
Language: Assembly - Size: 148 MB - Last synced at: 2 months ago - Pushed at: about 8 years ago - Stars: 4 - Forks: 6
zyx7k/Y86-64-Processor
Sequential & Pipelined implementation of Y86-64 ISA in Verilog
Language: Verilog - Size: 1000 Bytes - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
Amey-Thakur/COMPUTER-ORGANIZATION-AND-ARCHITECTURE-AND-PROCESSOR-ARCHITECTURE-LAB
CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>
Language: C - Size: 152 MB - Last synced at: 2 months ago - Pushed at: about 1 year ago - Stars: 14 - Forks: 2
UOC-Assignments/uoc.ca.prac2
Computer Architectures - Practical Assignment #2:
Language: C - Size: 137 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0
kejriwalrahul/3-Stage-Pipeline
A Three Stage Pipeline 16-bit processor implemented in Verilog
Language: Verilog - Size: 445 KB - Last synced at: 21 days ago - Pushed at: about 8 years ago - Stars: 4 - Forks: 3
onegentig/VUT-FIT-INP2022-projekt1 📦
První projekt (CPU s brainfuck-like ISA) z předmětu Návrh počítačových systémů (INP), třetí semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2022/2023
Language: VHDL - Size: 2.42 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
IndianMax03/toy-processor
Implementation of the processor model
Language: Python - Size: 1.38 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
Shahriar-0/Computer-Architecture-Lab-Experiments-F2023
ARM processor pipeline implementation, hazard unit, forwarding unit, SRAM & cache memory.
Language: Verilog - Size: 41.1 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
arxiver/Pipelined-MIPS
MIPS Pipelined CPU simulation using VHDL language
Language: VHDL - Size: 1.53 MB - Last synced at: 4 days ago - Pushed at: about 5 years ago - Stars: 6 - Forks: 0
PedroGrossi/Arquitetura-de-Computadores Fork of Pedro-Gros/Arquitetura-de-Computadores
Desenvolvimento de um processador simples em VHDL e implementação na FPGA - Disciplina de Arquitetura de computadores - 2023-2
Language: VHDL - Size: 17.3 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
ShichenQiao/ECE554_SP23_FPGA_Handwriting_Recognition 📦
Senior Design Project at UW-Madison ECE
Language: Verilog - Size: 91.1 MB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 6 - Forks: 0
Sooryakiran/Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project
Domain Specific Hardware Accelerators - VLSI CAD Project
Language: Bluespec - Size: 4.59 MB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 2
harmim/vut-avs-labs
Architektury výpočetních systémů - Cvičení
Language: C++ - Size: 3.63 MB - Last synced at: 2 months ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0
lazyoracle/vhdl-processor
An 8-bit processor in VHDL based on a simple instruction set
Language: VHDL - Size: 209 KB - Last synced at: 12 months ago - Pushed at: over 6 years ago - Stars: 5 - Forks: 0
trexxet/virtaxy-vm
Flexible functional simulator and assembler for user-defined architectures
Language: C - Size: 179 KB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 6 - Forks: 0
streetdogg/mips-cpu
Verilog implementation of a subset of MIPS 32 Bit Processor Instructions, ISA design, Assembler Design and Compiler design
Language: Verilog - Size: 98.6 KB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 1
npalmer5620/razor_cpu
RISC-V RV32I CPU core in SystemVerilog
Language: SystemVerilog - Size: 16.6 KB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0
tugrul512bit/AdvancedMacroDevices
2D RPG/RTS/Simulation game that lets you design a CPU & manage your corporation against other corporations.
Language: C++ - Size: 8.48 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
alumpish/CA-Lab-Projects
Projects of the computer architecture lab (Spring 02) at the University of Tehran.
Language: Verilog - Size: 13.9 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
helen1032/ITSC_2181
Introduction to computer system abstractions reflected in programming languages, operating systems, architectures, and networks. Topics include: overview of computer and processor architecture, instruction set architecture and introduction to assembly language, C programming, system calls, processes and process memory layout, interfaces for memory
Language: C - Size: 31.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
arda-guler/TurnaCore
An imaginary 16-bit CPU architecture with custom assembly language and instructions
Language: Python - Size: 9.14 MB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 0
linguini1/gol-16
A custom 16-bit processor with a custom assembly language and emulator, based off of the ARM 32-bit processor.
Language: C - Size: 512 KB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 5 - Forks: 0
nimaiji/MIPS-Pipeline-CPU
💻 MIPS Pipeline Processor simulator
Language: Python - Size: 313 KB - Last synced at: almost 2 years ago - Pushed at: almost 5 years ago - Stars: 3 - Forks: 0
phillipstanleymarbell/sunflower-simulator-gui
GUI for the Sunflower embedded microarchitectural simulator / full-system emulator.
Language: Limbo - Size: 31.1 MB - Last synced at: almost 2 years ago - Pushed at: over 9 years ago - Stars: 1 - Forks: 1
DeimosProject/Controller 📦
Language: PHP - Size: 88.9 KB - Last synced at: 22 days ago - Pushed at: about 8 years ago - Stars: 0 - Forks: 0
ramiil/smpa
Simple MicroProcessor Architecture - Tiny 8 bit CPU
Language: Python - Size: 5.86 KB - Last synced at: almost 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0
cfgnunes/homework-microprocessor
A risc microprocessor (uRisc) emulator made with C++.
Language: C++ - Size: 79.1 KB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
MisaghM/Computer-Architecture-Lab-Projects
ARM processor implementation, hazard unit, forwarding unit, SRAM & cache memory.
Language: Verilog - Size: 10.2 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
kiriware/Logisim-16-bit-RISC-Processor
Logisim implementation of a 16-bit single cycle and pipelined RISC processor designed from an instruction set.
Size: 2.82 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
SantoshSrivatsan24/single_cycle_datapath
Implementation of a single cycle datapath for an 8-bit RISC V processor with a reduced instruction set.
Language: Verilog - Size: 109 KB - Last synced at: almost 2 years ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 0
SantoshSrivatsan24/pipelined_datapath
Implementation of a pipelined datapath for a 32-bit RISC V processor with a reduced instruction set.
Language: Verilog - Size: 89.8 KB - Last synced at: almost 2 years ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 0
kiriware/16-bit-RISC-Processor-Logisim
WIP Logic level implementation of a 16-bit processor in Logisim.
Size: 367 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
samiyaalizaidi/Pipelined-RISC-V-Processor
A Pipelined RISC-V Processor with forwarding support and hazard detection.
Language: Verilog - Size: 79.1 KB - Last synced at: 3 months ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
ctsiaousis/mipsMultiCycleProcessor 📦
A VHDL implementation of a MIPS processor with multicycle instruction fetching
Language: C - Size: 1.36 MB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 0
damieng/binarycpu
Identify the processor architecture of binary files
Language: JavaScript - Size: 10.7 KB - Last synced at: about 21 hours ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0
zavierferodova/Computation-Challenge
Python script to fill your computer memory with processor bits word size
Language: Python - Size: 2.93 KB - Last synced at: 4 months ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
AugusteLef/Intel-Kaby-Lake
Simulation of an Intel Kaby lake cache coded in C
Language: C - Size: 604 KB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0
junior-jl/riscv-processor-model
A Python model for a RISC-V Single Cycle Processor and simple Assembler
Language: Python - Size: 486 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0
