GitHub topics: forwarding-unit
Mahekkumar-Varasada/5-Stage-MIPS-Pipelined-with-Hazard-Mitigation
The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Arithmetic Logical Unit (ALU) for basic operation, a forwarding unit and hazards detecting unit.
Language: Verilog - Size: 75.2 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0
nxbyte/ARM-LEGv8
Verilog Implementation of an ARM LEGv8 CPU
Language: Verilog - Size: 3.96 MB - Last synced at: 5 months ago - Pushed at: over 6 years ago - Stars: 97 - Forks: 29
FrenzyExists/Computer-Architecture-Project-SPARC
Final Project of the Computer Architecture (ICOM4215) course, Spring 2023. The project documents the journey of three students learning the basics of the vast world of FPGAs and hardware design in general. Here We designed a SPARC-Based Processor in Verilog :D
Language: Verilog - Size: 9.55 MB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 5 - Forks: 0
Shahriar-0/Computer-Architecture-Lab-Experiments-F2023
ARM processor pipeline implementation, hazard unit, forwarding unit, SRAM & cache memory.
Language: Verilog - Size: 41.1 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0
MisaghM/Computer-Architecture-Lab-Projects
ARM processor implementation, hazard unit, forwarding unit, SRAM & cache memory.
Language: Verilog - Size: 10.2 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
mhyousefi/MIPS-pipeline-processor
A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
Language: Verilog - Size: 1.54 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 95 - Forks: 27
arianhaddadi/ARM-Processor-32-bit
A 32-bit Arm Processor Using Verilog HDL With Hazard Detection, Forwarding Unit, SRAM Memory & A 2-Way Set-Associative Cache.
Language: Verilog - Size: 686 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0
