Mahekkumar-Varasada/5-Stage-MIPS-Pipelined-with-Hazard-Mitigation

The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Arithmetic Logical Unit (ALU) for basic operation, a forwarding unit and hazards detecting unit.

Language: Verilog - Size: 75.2 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0