GitHub / astrogeekdk / RISC-V-Basic-SIMD
A basic implemention of 8 lane vector SIMD in RISC-V 5 Stage Pipeline, written in Chisel and Scala.
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PURL: pkg:github/astrogeekdk/RISC-V-Basic-SIMD
Stars: 0
Forks: 0
Open issues: 0
License: None
Language: Scala
Size: 12.7 KB
Dependencies parsed at: Pending
Created at: 4 months ago
Updated at: 4 months ago
Pushed at: 4 months ago
Last synced at: 3 months ago
Topics: processor, processor-architecture, processor-design, processor-simulator, risc-v, risc-v-assembly, risc-v-emulator, simd, simd-parallelism