GitHub / GeekAlexis / superscalar-mips

A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/GeekAlexis%2Fsuperscalar-mips
PURL: pkg:github/GeekAlexis/superscalar-mips

Stars: 10
Forks: 3
Open issues: 0

License: None
Language: Verilog
Size: 47.1 MB
Dependencies parsed at: Pending

Created at: over 6 years ago
Updated at: 6 months ago
Pushed at: almost 6 years ago
Last synced at: 6 months ago

Topics: mips, processor-architecture, verilog

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