GitHub / VadanShah / 3-Stage-ALU-Pipeline-Processor

🚀 Verilog-based 3-stage pipelined ALU processor supporting ADD, SUB, AND, OR, MUL (Booth’s), and DIV (Restoring) operations.

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PURL: pkg:github/VadanShah/3-Stage-ALU-Pipeline-Processor

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Created at: 3 months ago
Updated at: 3 months ago
Pushed at: 3 months ago
Last synced at: 3 months ago

Topics: computer-architecture, pipeline, processor-architecture, processor-design

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