katamaran-project/katamaran

Katamaran is a semi-automated separation logic verifier for the Sail specification language. It works on an embedded version of Sail called μSail and verifies separation logic-based contracts of functions by generating (succinct) first-order verification conditions.

Language: Coq - Size: 6.78 MB - Last synced at: about 15 hours ago - Pushed at: about 16 hours ago - Stars: 18 - Forks: 5

Simulacrum0/Simulacrum0.github.io

Wantware Deployment Website

Language: HTML - Size: 54.2 MB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 0 - Forks: 0

notdroplt/Supernova

Zenith runtime virtual machine

Language: Zig - Size: 142 KB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 2 - Forks: 0

AluVM/aluvm

AluVM: RISC functional machine base implementation

Language: Rust - Size: 1.42 MB - Last synced at: 2 days ago - Pushed at: 12 days ago - Stars: 61 - Forks: 23

ryukzak/wrench

Wrench - is a tool for educating computer architecture.

Language: Haskell - Size: 537 KB - Last synced at: 12 days ago - Pushed at: 12 days ago - Stars: 7 - Forks: 16

player400/pi

My very own CPU architecture! Emulator availible!

Language: C++ - Size: 368 KB - Last synced at: 15 days ago - Pushed at: 16 days ago - Stars: 5 - Forks: 0

hlorenzi/customasm

💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/

Language: Rust - Size: 5.22 MB - Last synced at: 16 days ago - Pushed at: 16 days ago - Stars: 936 - Forks: 63

HrishikeshSuchindra/Process-In-Memory-ISA-Compiler

📦 PIM Compiler A lightweight compiler for a custom 24-bit Processor-In-Memory (PIM) Instruction Set Architecture. This tool translates simple C-like matrix operations into 24-bit machine instructions through parsing, intermediate representation (IR) generation, and custom microcode mapping.

Language: C - Size: 47.9 KB - Last synced at: 24 days ago - Pushed at: 26 days ago - Stars: 1 - Forks: 0

mikeroyal/AMX-Guide

Advanced Matrix Extensions (AMX) Guide

Language: C++ - Size: 44.9 KB - Last synced at: 8 days ago - Pushed at: over 3 years ago - Stars: 88 - Forks: 7

sjohann81/hf-risc

HF-RISC SoC

Language: C - Size: 5.16 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 32 - Forks: 36

Mariuspersen/cisc64

Idea for a new type of architecture

Language: Zig - Size: 71.3 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

xxas/mint

C++26 Custom Instruction Set Architecture Framework

Language: C++ - Size: 66.4 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

Alexia022/MIPS_Assembly_Programs

A comprehensive collection of MIPS assembly language programs demonstrating low-level programming concepts, algorithm implementation, and computer architecture principles through practical applications like calculators, pattern generators, and educational tools.

Language: Assembly - Size: 15.6 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

aofarmakis/Nibbling-bits

Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.

Language: Verilog - Size: 4.01 MB - Last synced at: about 1 month ago - Pushed at: 5 months ago - Stars: 32 - Forks: 0

david-palma/mips-32bit

Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.

Language: VHDL - Size: 366 KB - Last synced at: about 1 month ago - Pushed at: almost 6 years ago - Stars: 6 - Forks: 1

vrstanchevLab/ASMLab

Educational resources for learning NASM, GNU ASM, RISC-V assembly language, and C programming. Includes examples, tutorials, and hands-on exercises for mastering low-level systems programming.

Language: Assembly - Size: 318 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 3 - Forks: 0

mannasoumya/vm-go

Stack Based Virtual Machine in Golang

Language: Go - Size: 4.88 MB - Last synced at: about 1 month ago - Pushed at: 2 months ago - Stars: 9 - Forks: 3

adolan527/LC3-RTL

A Verilog implementation of the LC3 (Little Computer 3) micro-architecture/ISA as described in "Introduction to Computing Systems" by Patt & Patel.

Language: Verilog - Size: 13.2 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 1 - Forks: 0

wyxh2004/c-cpp-learning-snippets

Linux kernel / Algorithm / Instruction Set / Pointer / Makefile / Advanced C Programming

Language: C++ - Size: 155 KB - Last synced at: about 1 month ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

vrstanchev/Degrees

🎓 M.Sc. in Computer Systems & Technologies 📍 Technical University of Sofia – Plovdiv Branch 🛠️ Specialization: Advanced systems programming, low-level optimizations, Linux internals. 🎓 B.Sc. in Software Engineering 📍 Plovdiv University Paisii Hilendarski

Language: Assembly - Size: 25.3 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 2 - Forks: 0

TomerAberbach/mano-simulator

🖥️ An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer.

Language: Java - Size: 1.26 MB - Last synced at: 1 day ago - Pushed at: 7 months ago - Stars: 38 - Forks: 15

ewdlop/Hardware-Notes

Electrical Enignnering

Language: VHDL - Size: 69.8 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

Maratyszcza/Opcodes

Database of CPU Opcodes

Language: Python - Size: 6.55 MB - Last synced at: 8 days ago - Pushed at: about 1 year ago - Stars: 247 - Forks: 44

angrysky56/MetaTransformers-Fractal-Workflow-System

This repository contains the codebase for the MetaTransformers Fractal Workflow System, a comprehensive framework for managing and orchestrating complex workflows. The system is designed to handle a wide range of data types and workflows, from simple data processing to complex AI-driven transformations.

Language: Python - Size: 239 MB - Last synced at: 21 days ago - Pushed at: 4 months ago - Stars: 6 - Forks: 1

BrandonDao/ProjectISA

A C# assembler, disassembler, and emulator for my custom instruction set architecture (work in progress)

Language: C# - Size: 7.81 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

yonseicasl/Kite

Kite: Architecture Simulator for RISC-V Instruction Set

Language: C++ - Size: 2.82 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 14 - Forks: 5

david-palma/mips-32bit-encoder

C implementation of a 32-bit assembly instruction encoder for MIPS processors, designed to convert MIPS assembly instructions into their corresponding machine code formats for execution on MIPS-based systems.

Language: C - Size: 5.86 KB - Last synced at: about 2 months ago - Pushed at: almost 6 years ago - Stars: 0 - Forks: 0

edanor/umesimd

UME::SIMD A library for explicit simd vectorization.

Language: C++ - Size: 5.89 MB - Last synced at: 28 days ago - Pushed at: over 7 years ago - Stars: 91 - Forks: 16

omrawaley/txt-8

TXT-8 is a simple 8-bit text-based virtual machine with the intent of education on virtualization.

Language: C++ - Size: 43 KB - Last synced at: about 2 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

dmjio/LC3

:floppy_disk: The LC3 virtual machine

Language: Haskell - Size: 22.5 KB - Last synced at: 29 days ago - Pushed at: 5 months ago - Stars: 23 - Forks: 2

celebi-pkg/riscv-assembler

RISC-V Assembly code assembler package for Python.

Language: Assembly - Size: 344 KB - Last synced at: about 1 month ago - Pushed at: 8 months ago - Stars: 18 - Forks: 10

JBrosDevelopment/VirtualComputer

This project is a virtual computer that takes a vector of bytes and runs it as instructions. Also included is a complete assembler and compiler.

Language: Rust - Size: 36.4 MB - Last synced at: about 2 months ago - Pushed at: 8 months ago - Stars: 2 - Forks: 0

Layheng-Hok/RISC-V-CPU

RISC-V CPU: Single-Cycle Processor for RISC-V ISA Built in Verilog - SUSTech's project of course CS202: Computer Organization in Spring 2024 - Score: 104.5/100

Language: VHDL - Size: 25.1 MB - Last synced at: about 2 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 1

DivergentClouds/riw-16

A fantasy computer with 16 instructions.

Size: 46.9 KB - Last synced at: 2 months ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0

thacuber2a03/float

an attempt at writing a VM

Language: C - Size: 36.1 KB - Last synced at: 28 days ago - Pushed at: 7 months ago - Stars: 2 - Forks: 1

alirezakay/RISC-CPU

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Language: VHDL - Size: 2.52 MB - Last synced at: about 2 months ago - Pushed at: almost 4 years ago - Stars: 27 - Forks: 5

UserJHansen/Computer

Custom 32 bit computer

Language: TypeScript - Size: 297 KB - Last synced at: about 1 month ago - Pushed at: 9 months ago - Stars: 3 - Forks: 0

icarogabryel/sea-iv

SEA-IV is a simple assembler for the MOOn-IV architecture. It is written in Python 3 and is a command-line tool.

Language: Python - Size: 151 KB - Last synced at: about 2 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

mehmetakifkoz/MARS-Web-App

This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.

Language: JavaScript - Size: 25.4 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

Mograsim-Team/Mograsim

Modular Graphical Simulator for Teaching Microprogramming

Language: Java - Size: 4.5 MB - Last synced at: 4 days ago - Pushed at: 5 months ago - Stars: 12 - Forks: 1

agicy/buptAsgmt-organization 📦

北京邮电大学 2023-2024 春季学期《计算机组成原理》课程作业的相关文档

Size: 34.7 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0

MarinosSav/IJVM_Emulator

A programming project aimed at implementing an IJVM emulator using C.

Language: C - Size: 80.1 KB - Last synced at: about 2 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

sdasgup3/parallel-processor-design

Super scalar Processor design

Language: Verilog - Size: 137 KB - Last synced at: about 1 month ago - Pushed at: over 10 years ago - Stars: 21 - Forks: 3

ortanaV2/Custom-Assembly-Compiler

Compiles TIICBC Assembly Code into an 8x12bit Binary Instruction-Set .rc File.

Language: Python - Size: 8.79 KB - Last synced at: 3 days ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

mishqatabid/16-Bit-ISA-Simulator

ISA Simulator emulates basic ISA operations, managing memory, registers, and instruction execution

Language: C++ - Size: 13.7 KB - Last synced at: 3 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

Barracudapi/CPU-RISC-V

CS202 Project: Programming a RISC-V CPU in VHDL

Language: VHDL - Size: 24 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

izcoser/mips-computer

MIPS ISA simulation with Logisim Evolution.

Size: 464 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

danielegrazzini/DSM

DSM (Design Structure Matrix)

Size: 16.5 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

gabrieldim/Assembly-MIPS-Instruction-Set

Assembly program with the MIPS instruction set

Language: Assembly - Size: 3.91 KB - Last synced at: about 1 month ago - Pushed at: over 4 years ago - Stars: 99 - Forks: 1

iabdullah215/16-bit-Instruction-Set-Architecture-Simulator

Language: C++ - Size: 8.79 KB - Last synced at: 3 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

marceldobehere/MAAB-CPP-Interpreter

Language: C++ - Size: 357 KB - Last synced at: 2 months ago - Pushed at: about 1 year ago - Stars: 3 - Forks: 0

marceldobehere/goofy-cpu

a goofy 8 bit cpu

Language: C# - Size: 3.85 MB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 4 - Forks: 0

Roninkoi/RAMPE

RAMPE computer ISA with assembler and simulator

Language: Fortran - Size: 289 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

JohnMachado11/CS104-Computer-Architecture

Python implementation of a 32-bit processor with its own ISA (Instruction Set Architecture)

Language: Python - Size: 13.7 KB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

petabite/gomachine

A very basic CPU simulator

Language: Go - Size: 25.4 KB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

orbit-systems/aphelion

64-bit RISC CPU Architecture

Size: 4.31 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 12 - Forks: 0

rakshitharnayak/RISC--V-Processor

RISC V PROCESSOR DESIGN IN VERILOG

Language: Verilog - Size: 27.3 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Pritjam/pARMesan

A simple CPU architecture specification based on AArch64 and with a little x86 inspiration. Additionally, a C implementation of this architecture and an assembler written in Python.

Language: C - Size: 175 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

iaakash47/vsdriscv

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

Size: 72.3 KB - Last synced at: about 1 year ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

jamestiotio/compstruct

SUTD 2020 50.002 Computation Structures Code Dump

Language: C - Size: 89.7 MB - Last synced at: about 1 year ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 0

HarieshAnbalagan/RV32I

Minimalistic RV32I RISC-V Processor in System Verilog

Language: SystemVerilog - Size: 392 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

yehzhang/x9

9-bit ISA

Language: SystemVerilog - Size: 603 KB - Last synced at: about 2 months ago - Pushed at: almost 8 years ago - Stars: 0 - Forks: 1

AshleighAdams/Swis

Simple Wire Instruction Set

Language: C# - Size: 690 KB - Last synced at: 6 days ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 0

einhalv/ocparse

Python module to work with microprocessor instruction sets

Language: Python - Size: 42 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

jracevedob/RISC-ARA Fork of pulp-platform/ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

Language: Assembly - Size: 18.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

ArvinDelavari/Instruction-Set-Executant

C++ basic instruction set simulator

Language: C++ - Size: 25.4 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 1

hohaicongthuan/RV64IF 📦

RISC-V 64-bit with 32-bit floating point extension support.

Language: Verilog - Size: 14.6 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 0

anktjsh/Y86-Simulator

Y86 ISA Simulator and Virtual Machine

Language: Java - Size: 2.13 MB - Last synced at: over 1 year ago - Pushed at: almost 7 years ago - Stars: 2 - Forks: 0

patel-soham/16-bit-microprocessor-verilog

A final year undergraduate major project. (Dec 2019 - Mar 2020)

Language: C - Size: 3.06 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

Fhoughton/ToyVM

A small toy VM and assembler written in python as a learning exercise. Has 3 registers, with storage, maths and printing.

Language: Python - Size: 3.91 KB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0

brianfakhoury/Fast-Inverse-Square-Root-Magic-Number-Optimization

Testing out optimal magic numbers for the old fast inverse square root function.

Language: Python - Size: 170 KB - Last synced at: over 1 year ago - Pushed at: almost 6 years ago - Stars: 0 - Forks: 0

kbecke05/CPE315-Computer-Architecture

A collection of old projects in assembly and Java from class assignments

Language: Java - Size: 58.6 KB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

kbecke05/CSC225-Computer-Organization

A collection of assembly files written for class assignments

Language: Assembly - Size: 19.5 KB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

nhays89/PC-sim

c assembler & data path simulator implementing the LC-2200 ISA.

Language: C - Size: 1.51 MB - Last synced at: almost 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

Paxsma/ISCreator

Create and represent instruction sets in code easily.

Language: C++ - Size: 11.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

IsaacSteadman/StackVM

A 64-bit stack based instruction set architecture definition with reference implementation. (The assembler is part of my C compiler that targets StackVM)

Language: Python - Size: 142 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

beyzanc/18-bit-processor-implementation-using-logisim

18-bit processor implementation using Logisim

Language: Python - Size: 530 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

lthoerner/smis

A project to create a basic instruction set for simple implementation and simple coding.

Language: C - Size: 1.44 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

nnk03/PIPELINE-GROUP-13-BATCH-2021-CO-LAB-IIT-PALAKKAD

Pipelining using Verilog done during the Computer Organisation and Architecture Lab during Semester 3

Language: Verilog - Size: 5.45 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

farkoo/farkoo-Simulator

An assembler and hardware simulator for Mano Basic Computer, a 16-bit computer.

Language: C# - Size: 262 KB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 4 - Forks: 0

Sacusa/MoCha

A pedagogical processor on FPGA, developed at NIIT University.

Language: VHDL - Size: 798 KB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 3 - Forks: 1

techieforfun/mipsimulator

:control_knobs: Simulator for the Single Cycle MIPS Processor

Language: C++ - Size: 3.44 MB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 0 - Forks: 0

fgmn/Computer-Organization-Course-Design

SDU 20级计科计组课设

Language: VHDL - Size: 25.8 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 2 - Forks: 0

iwdgo/processorfeatures

Processor features

Language: Go - Size: 160 KB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

kcelebi/riscv-assembler

RISC-V Assembly code assembler package for Python.

Language: Python - Size: 1.77 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 41 - Forks: 12

mohdfahad12328/scpu

a smiple 8bit cpu implemented in verilog and tested on FPGA for understanding how CPU works

Language: Verilog - Size: 1.77 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

spsandwichman/aphelion16

custom 8/16-bit instruction set architecture

Language: Nim - Size: 487 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

Danila-Pechenev/InstructionAnalysisFramework

Framework for collecting and analyzing data on the use of machine instructions

Language: Jupyter Notebook - Size: 230 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 1

Jacopo00811/02135_Introduction_to_Cyber_Systems

02135 Introduction to Cyber Systems Spring 22 DTU

Language: Python - Size: 1.73 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

Didula98/Building-a-Simple-Processor

Simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL

Language: Verilog - Size: 7.97 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 5 - Forks: 0

zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

Language: Verilog - Size: 1.51 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 62 - Forks: 26

Casparvolquardsen/Mikrorechner

Dieses Repository enthält die Implementierung eines RISC Prozessors mit VHDL, welche im Rahmen eines Projekts an der Universität Hamburg entstanden ist.

Language: VHDL - Size: 483 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 4 - Forks: 0

scarv/xcrypto

XCrypto: a cryptographic ISE for RISC-V

Language: Verilog - Size: 2.03 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 81 - Forks: 10

VenkatKS/CHIP8

Full graphical instruction-level emulator for the CHIP-8 Instruction Set Architecture

Language: C - Size: 146 KB - Last synced at: about 2 years ago - Pushed at: almost 8 years ago - Stars: 2 - Forks: 0

arsalanyavari/mano-simulator

An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer

Language: C++ - Size: 69.7 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 1

moonheart08/SERAIS 📦

Space Efficient RISC Architecture and Instruction Set

Language: Assembly - Size: 164 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

aditiisaxena/Assembler-Simulator

A program that converts assembly code to binary and further simulates it to run the program as required

Language: Python - Size: 88.9 KB - Last synced at: about 1 month ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

scarv/scarv-cpu

SCARV: a side-channel hardened RISC-V platform

Language: Verilog - Size: 1.37 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 18 - Forks: 6

keneoneth/InstrHexBinDecConvertDecoder-Release

a web based front end only helper tool that provides Instruction Decoder and Converter in hexadecimal binary decimal form encoding of different ISA

Language: HTML - Size: 699 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

wisk/isabelle

Instruction Set Architecture Description Format

Language: Python - Size: 211 KB - Last synced at: about 2 years ago - Pushed at: over 8 years ago - Stars: 6 - Forks: 3