AlonMell/build-a-computer

Implementation of a modern computer system from first principles. Starting with basic NAND gates and progressively building a CPU

Language: Hack - Size: 61.5 KB - Last synced at: 11 days ago - Pushed at: 14 days ago - Stars: 0 - Forks: 0

bsod2528/cpu

a simple risc processor

Language: Verilog - Size: 126 KB - Last synced at: 15 days ago - Pushed at: 15 days ago - Stars: 0 - Forks: 0

phoeniX-Digital-Design/phoeniX

RISC-V Embedded Processor for Approximate Computing

Language: Verilog - Size: 160 MB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 124 - Forks: 82

mrFavoslav/4bit-cpu-emulator

4bit CPU Emulator – A simple 4-bit processor emulator written in JavaScript. Run assembly code directly in your browser! Perfect for learning the basics of computer architecture and low-level programming.

Language: JavaScript - Size: 25.4 KB - Last synced at: 22 days ago - Pushed at: 23 days ago - Stars: 0 - Forks: 0

eon0111/RISC-V-CPU

This is my master's degree final thesis. I'll be adding pipelining capabilities to an existing RISC-V single cycle design

Language: Scala - Size: 44.5 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 0 - Forks: 0

BrentSeidel/VHDL-CPU

VHDL Design for a CPU

Language: C - Size: 3.16 MB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

arsalanjabbari/RISCV-CPU-Design

In this project, you will be tasked with implementing pipeline registers and connecting all the modules you've created so far to build a complete RISC-V processor. The successful completion of this project will result in a functional MIPS processor, and you'll have the opportunity to gain bonus points by handling hazards.

Language: Verilog - Size: 8.79 KB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 1

rauhul/ece411

Computer Architecture UIUC SP 2018

Language: Assembly - Size: 81.8 MB - Last synced at: 9 days ago - Pushed at: almost 7 years ago - Stars: 12 - Forks: 2

TamaGo-HQ/cave_cpu

a primitive cavecpu for primitive cavemen

Size: 0 Bytes - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

Karan-nevage/RISC-V-Single-Cycle-Core-Verilog-

This project involves designing a single-core RISC-V CPU using Verilog. The design includes an Arithmetic Logic Unit (ALU) with flags, an assembly to machine code converter, a control unit, a microarchitecture and memory initialization to ensure proper functioning of the CPU.

Language: JavaScript - Size: 1.07 MB - Last synced at: 2 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 1

mehmetakifkoz/MARS-Web-App

This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.

Language: JavaScript - Size: 25.4 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

q-datum/Single-Cycle-RISC-V-Processor

RV32I architecture implemented in Verilog

Language: Verilog - Size: 14.6 KB - Last synced at: 9 months ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

RyBlue29/Duck-Hunt

These files make up my home made processor in Verilog. I simulated my processor on an FPGA to create an arcade style duck hunt game!

Language: Verilog - Size: 22.7 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

loypt/computer-hardware-design

Hust Courses for learning Computer hardware design,also It's the experiment of COA（Computer Organization and Architecture）

Size: 13 MB - Last synced at: 12 months ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

SimonBuxx/Linkuit-Studio

A platform for learning and experimenting with logic circuits

Language: C++ - Size: 3.21 MB - Last synced at: 12 months ago - Pushed at: about 1 year ago - Stars: 19 - Forks: 2

FISC-Project/FISC-SystemVerilog

FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64

Language: Verilog - Size: 90.8 KB - Last synced at: about 1 year ago - Pushed at: over 5 years ago - Stars: 5 - Forks: 1

FISC-Project/FISC-Microlang

FISC-Microlang is a low level language below Assembly. It is used in the FISC project for creating the Microcode memory.

Language: M4 - Size: 3.02 MB - Last synced at: about 1 year ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 0

arsalanjabbari/MIPS-CPU-Design

This project involves the creation of a single-cycle MIPS CPU design using Verilog. The single-cycle microarchitecture is characterized by executing an entire instruction in one clock cycle. The project delves into the intricacies of designing and implementing a simplified MIPS CPU, providing insights into its fundamental components.

Language: Verilog - Size: 8.79 KB - Last synced at: 2 months ago - Pushed at: over 1 year ago - Stars: 5 - Forks: 0

MinecraftPublisher/bit

A simple, Turing-complete and easy to recreate CPU architecture.

Language: HTML - Size: 1.04 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

martandrMC/cpu-design

This repository contains files regarding my CPU designs

Language: Verilog - Size: 8.33 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 0

mrmcsoftware/CPUsimulator

This is an HTML/Javascript CPU simulator and assembler for the CPU I designed. Originally, I created this CPU on paper many years ago for a homework assignment in college. More recently, I implemented my design in the Logisim logic simulator, and eventually it ran on an FPGA.

Language: HTML - Size: 884 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 16 - Forks: 0

mrmcsoftware/MyCPUfiles

These are various files pertaining to a CPU I designed. Can be used in conjunction with my Logisim CPU youtube video series.

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ArvinDelavari/Digital-Circuits-Verilog

Sample Verilog codes for digital circuits

Language: HTML - Size: 9.31 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0

joonicks/BizzasCPU

Bizzas CPU design

Language: C - Size: 423 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

phoeniX-Digital-Design/.github

Size: 188 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

marcotulio956/boring.cyclesLAOCII

Language: Verilog - Size: 219 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

SamEThibault/elec-374

Verilog CPU Design Project, ELEC 374 - Digital Systems Engineering

Language: Verilog - Size: 223 KB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

ArvinDelavari/RV32-APX

32 Bits RISC-V Processor with Approximate Functions

Language: Verilog - Size: 140 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0

naderabdalghani/32-bit-risc-pipelined-processor

Implementation of a simple 5-stage 32-bit pipelined processor and its assembler using VHDL and Python

Language: VHDL - Size: 18.1 MB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 2 - Forks: 4

fgmn/Computer-Organization-Course-Design

SDU 20级计科计组课设

Language: VHDL - Size: 25.8 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 2 - Forks: 0

Russellwzr/Design-and-implementation-of-a-simple-CPU

Design-and-implementation-of-a-simple-CPU

Language: VHDL - Size: 35.8 MB - Last synced at: about 2 months ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

MarkArranz/nand2tetris

Building a computer from first principles. Logic Gates -> CPU Architecture -> Machine Language -> VM -> High-Level Language -> Compiler -> OS -> DS & A

Language: Hack - Size: 729 KB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

emmapaczkowski/ELEC374

The purpose of this project is to design, simulate, implement, and verify a simpleRISC Computer (Mini SRC) consisting of a simple RISC processor, memory, and I/O.

Language: Verilog - Size: 115 KB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 5 - Forks: 3

ChaminduS/Building-a-RISC-V-CPU-Core

This repository contains my work in completing the course titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX.

Size: 175 KB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 0

EmreKumas/Processor_Design 📦

This is an implementation of a simple CPU in Logisim and Verilog.

Language: Verilog - Size: 171 KB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 4 - Forks: 0

OrangeBacon/orange

Emulator for custom computer architecture

Language: C - Size: 1.34 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 4 - Forks: 2

sarthi92/cpu_cisc

Verilog implementation of 8-bit CISC Processor using 4 phase clocking scheme

Language: Verilog - Size: 72.3 KB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 3 - Forks: 1

sarthi92/vector_processor

Design of Banked Memory Access Unit for Load Store Instructions of a 32-bit Vector Processor

Language: Verilog - Size: 5.86 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 8 - Forks: 3

VahidHeidari/CPU-E-bity

4-bit CPU designed with discrete components and 74-series ICs.

Language: HTML - Size: 1.72 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

arashsm79/mips-hdl

Single-cycle and multi-cycle implementation of a subset of MIPS instruction set

Language: Verilog - Size: 504 KB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

khoek/komputer

A computer I'm building from scratch out of ICs

Language: Prolog - Size: 21.4 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 0

moreda-a/CPU-Design-RISC

Computer Architecture Project

Language: VHDL - Size: 453 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

sarthi92/cpu_risc

Verilog implementation of 16-bit RISC Processor with 4-stage pipeline

Language: Verilog - Size: 51.8 KB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 0 - Forks: 1