GitHub / q-datum / Single-Cycle-RISC-V-Processor
RV32I architecture implemented in Verilog
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License: mit
Language: Verilog
Size: 14.6 KB
Dependencies parsed at: Pending
Created at: over 2 years ago
Updated at: 9 months ago
Pushed at: over 2 years ago
Last synced at: 9 months ago
Topics: cpu-design, risc-v, verilog
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