GitHub topics: address-memory
EmreKumas/Processor_Design 📦
This is an implementation of a simple CPU in Logisim and Verilog.
Language: Verilog - Size: 171 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 4 - Forks: 0
This is an implementation of a simple CPU in Logisim and Verilog.
Language: Verilog - Size: 171 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 4 - Forks: 0