NellyW8/VeriReason

This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Language: Python - Size: 272 KB - Last synced at: 9 days ago - Pushed at: 19 days ago - Stars: 5 - Forks: 1

jge162/verilog_compiler

Verilog_Compiler is now available in GitHub Marketplace! This tool can quickly compile Verilog code and check for errors, making it an essential tool for developers.

Language: Verilog - Size: 520 KB - Last synced at: 2 days ago - Pushed at: 8 months ago - Stars: 15 - Forks: 0

geraked/verilog-rle

Verilog Implementation of Run Length Encoding for RGB Image Compression

Language: Verilog - Size: 11.6 MB - Last synced at: about 2 months ago - Pushed at: about 4 years ago - Stars: 25 - Forks: 4

VLSIJEXA/System-Verilog

learning system verilog

Language: SystemVerilog - Size: 17.6 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

HMarchiori/controle-microondas-verilog

Este projeto em Verilog implementa dois módulos principais para controle de um timer, componente de um sistema de microondas. O microondas contém uma máquina de estados finitas, controle lógico para ativação, pausa, e finalização, bem como controle de potência, ativada por meio de controles físicos.

Language: Tcl - Size: 9.77 KB - Last synced at: 17 days ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

benitoss/UnAmiga

Implementation of Amiga 500/1200 in Altera Cyclone IV FPGA

Language: VHDL - Size: 267 MB - Last synced at: 3 months ago - Pushed at: about 6 years ago - Stars: 52 - Forks: 6

TheSUPERCD/8bit_MicroComputer_Verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

Language: Verilog - Size: 173 KB - Last synced at: 3 months ago - Pushed at: over 2 years ago - Stars: 54 - Forks: 15

ridhimach12/VHDL

This repository contains various Verilog implementations of fundamental digital circuits.Each module is tested with a corresponding Testbench for simulation in EDA Playground

Language: Verilog - Size: 45.9 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

Foynguyn/CE213_HDL

My homework in HDL class

Language: Verilog - Size: 29.3 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

ubyhzargam/Verilog

These are Verilog (HDL) codes.

Language: Verilog - Size: 208 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

Amritamaya/MATRIX-INVERSE-VERILOG-nxn

This repository contains a Verilog implementation of matrix inversion using the Gaussian-Jordan elimination method. The module supports fixed-point arithmetic for better numerical precision and is parameterized to handle different matrix sizes and bit widths.

Size: 2.93 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

MohammedS2lah/HDLBits_Verilog_Tutorials

Welcome to my repository, where I provide solutions to Verilog challenges from the HDLBits website

Language: Verilog - Size: 378 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

aut-ce/CE202-LC-Lab-Manual

Manual and Template Sources of Logic Circuit Laboratory (Verilog Templates)

Language: C - Size: 80.1 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 16 - Forks: 22

kazutomo/Chisel-DE1SOC-FPGA-template

A template Chisel project for the DE1SOC FPGA board

Language: Scala - Size: 5.86 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 1

anarayandev/Verilog-Projects

Projects using Verilog Language

Size: 970 KB - Last synced at: about 2 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

shrujan0274/HDLBits-submissions

Solutions for 100+ questions in HDLBits using verilog

Language: Verilog - Size: 37.1 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

siri-n-shetty/iverilog

This repository contains a series of Verilog codes for the course UE22CS251A (DDCO).

Language: Verilog - Size: 9.26 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 13 - Forks: 5

aditeyabaral/DDCO-Lab-UE18CS207

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

Language: Verilog - Size: 1.82 MB - Last synced at: 4 months ago - Pushed at: about 5 years ago - Stars: 16 - Forks: 9

samiyaalizaidi/Direct-Digital-Synthesizer

Direct Digital Synthesizer for Generating Sine Waves using Verilog HDL

Language: Verilog - Size: 220 KB - Last synced at: 4 months ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

chrnthnkmutt/CarPark_Verilog

This project is using for illustrating on making the circuit on Xillin's BASYS3 from AMD and Verilog Language on Vivado, on the scope of car parking system

Language: Verilog - Size: 37.1 KB - Last synced at: 4 months ago - Pushed at: 9 months ago - Stars: 1 - Forks: 1

mahdizynali/verilog-digital-circuit-codes

simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)

Language: Verilog - Size: 13.7 KB - Last synced at: 4 months ago - Pushed at: about 2 years ago - Stars: 8 - Forks: 1

VLSIJEXA/basic-VHDL

VHDL Implementations:logic Gates, Flip-Flops, Adders, Mux, and Encoders/Decoder This repository contains VHDL implementations of essential digital circuits used in FPGA and ASIC design .This repository is useful for digital design projects and for understanding different VHDL modeling styles: behavioral, structural, and dataflow.

Language: C - Size: 8.52 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 1 - Forks: 0

yuri-panchul/tt08-adder-with-flow-control Fork of TinyTapeout/tt08-verilog-template

Submission for Tiny Tapeout 8 - Verilog HDL Projects. An adder with a separate flow control for each argument and the result.

Language: SystemVerilog - Size: 43.9 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 3 - Forks: 1

hwlabnitc/hwlabnitc.github.io

Main website of the HW Lab guide by NITC

Size: 24.6 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 2 - Forks: 4

camilaqPereira/oficina-verilog-siecomp

Neste repositório estão disponibilizados todos os arquivos utilizados na Oficina Introdução ao Verilog Comportamental ministrado na XXXI SIECOMP (UEFS). Além disso, estão listados múltiplos recursos para estudo da linguagem.

Language: Verilog - Size: 950 KB - Last synced at: 3 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

vSasakiv/RV32I_Processor

Risc-V 32i processor written in the Verilog HDL

Language: Verilog - Size: 6.61 MB - Last synced at: 8 months ago - Pushed at: over 2 years ago - Stars: 6 - Forks: 0

foodinsect/Advanced-Practice

This repository contains a collection of small Verilog modules for various purposes.

Language: Verilog - Size: 181 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

GirloftheLimberlost/DigitalLockFPGA

FPGA Digital Lock System with 7 Segment LED Display - Password changeable (Hexadecimal Passwords)

Size: 721 KB - Last synced at: 11 months ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 2

amirah-sri/all_verilog

I am trying to develop my skills through daily practice and consistency.

Language: Verilog - Size: 735 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

EhsanShahbazii/Digital-VLSI-System-Design-Projects 📦

سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر

Language: Verilog - Size: 73.2 KB - Last synced at: 4 months ago - Pushed at: over 1 year ago - Stars: 7 - Forks: 0

utkarshad21/FSM-Sequence-Detector-using-Verilog

FSM: Sequence Detector using Verilog HDL

Language: Verilog - Size: 2.93 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

utkarshad21/4-bit-Full-Adder-using-Verilog-HDL

Verilog code and testbench for 4-bit full adder

Language: Verilog - Size: 5.86 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

YajanaRao/Verilog

Verilog Programs

Language: Verilog - Size: 133 KB - Last synced at: 6 days ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 0

daringpatil3134/SPI_Serial_Peripheral_Interface_Verilog_Modules

Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device

Language: Verilog - Size: 29.3 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 5 - Forks: 2

Sanskar777/QRS-peak-detection-in-ECG-signals-using-verilog

Language: Verilog - Size: 8.79 KB - Last synced at: 4 months ago - Pushed at: over 5 years ago - Stars: 9 - Forks: 2

aaronrjmanj/verilog

This is my HDL code page which I started to showcase my coding skills and documenting my work for future reference. I am pursuing my master's at Texas A&M University (2019-21). I am looking forward to be a verification engineer. If you have any doubts you are welcomed to email me @ [email protected]

Language: Verilog - Size: 567 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

Rudra-Joshi-002/Verilog_Codes

This Repository shows the implementation and results of various codes that I write in Verilog HDL

Language: Verilog - Size: 19.2 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Erfangholiz/My-VHDL

A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.

Language: Verilog - Size: 383 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

p4r4xor/verilog-labs

Pin-point analysis of the questions given in labs using FPGA and ASIC design.

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ddurfeeEngineer/System-Verilog-Tutorial-LFSR-

simple system verilog example using an LFSR as the application

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shilinti/Asynchronous-Interface

The asynchronous interface is spercifically designed for scalable parallel datapaths.

Language: Verilog - Size: 41 KB - Last synced at: about 1 year ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

ntuifranklin/ENES-246

Language: JavaScript - Size: 3.52 MB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

JN513/estudos_verilog

Exemplos feito em verilog para estudos

Language: Verilog - Size: 10.6 MB - Last synced at: 3 months ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

Raveem13/HDLbits-practice-solution

This is a repository containing my solutions to the problem statements given on HDLBits website.

Language: Verilog - Size: 150 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

dhwanish-3/Verilog-Programming-Logic-Design-Lab

Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator

Language: Verilog - Size: 28.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

TAKE72K/HDLPractice

Repo of my HDL exercises

Language: Verilog - Size: 110 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

mseminatore/fpgacoding

Source code companion to the fpgacoding.com blog

Size: 72.3 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 0

ARohithReddy/multiplier

Digital circuit description to perform multiplication with data_path and control_path using verilog

Language: Verilog - Size: 155 KB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 1

SatyenderYadav/verilog-code

These are verilog codes for the different ICs

Language: Verilog - Size: 596 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 1

wasifijaz/Digital-System-Design-Verilog-Implementation

Digital System Design Verilog Implementation

Language: Verilog - Size: 48.8 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

mongrelgem/UART-RTL-Physical-Design

Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2

Language: Perl - Size: 1.61 MB - Last synced at: 5 months ago - Pushed at: almost 6 years ago - Stars: 4 - Forks: 3

Sumit0976/Traffic-Light-Controller

Traffic Light Controller using Verilog done in Vivado

Language: Verilog - Size: 60.5 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Sumit0976/Schoolbook-Multiplications

This project is done in Vivado in Verilog with hardware implementation and the project is optimized Schoolbook multiplier which is much faster than the traditional ones

Language: Verilog - Size: 77.1 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Sumit0976/-Karatsuba-Algorithm

2-Term Karatsuba and 3-Term Karatsuba Algorithm on FPGAs in Vivado using Verilog with diffrent bits and with 3 diffrent method.

Size: 5.86 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Dhruv0Upadhyay/100_Days_of_RTL

100 Days challenge to improve digital desinging using languages like Verilog & SystemVerilog

Language: Verilog - Size: 1.05 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 0

pratikbhuran/Voting_Machine

Voting machine implemented in verilog

Language: Verilog - Size: 146 KB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 5 - Forks: 1

aula9/Computer-Design-of-Electronic-Circuits-Lectures

Size: 12.2 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

sumitarohit/Array_Multiplier_project

This is a 4*4 Array_Multiplier_project using Verilog HDL. This is successfully implemented on FPGA board.

Language: Tcl - Size: 179 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Arjun-Narula/Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

Language: JavaScript - Size: 2.07 MB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 29 - Forks: 7

janilaunonen/iCEblink40-examples

Simple example programs for the Lattice iCEblink40-HX1K Evaluation Kit in Verilog for fun and learning.

Language: Verilog - Size: 23.4 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

kaushikbaidya09/Verilog_Code

Hardware Modeling Using Verilog

Language: Verilog - Size: 185 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

SagarDevAchar/endmodule

Open Source Verilog Modules

Language: Verilog - Size: 52.7 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Code-Sample-Collection/VerilogHDL-Practical-insights

<轻松成为设计高手: VerilogHDL 实用精解> EDA 先锋工作室, 王诚, 吴继华 2012.6

Language: Verilog - Size: 269 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

djzenma/RV32IC-CPU

Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

Language: Verilog - Size: 3.19 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 11 - Forks: 2

AlPrime2k1/Sequential-Logic-Circuits

Verilog design and testbench files for Flip Flop, Counters, RAM, FIFO, Shift Registers and other sequential logic circuits

Language: Verilog - Size: 22.5 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

nitindinnu/verilogg

This repository contains verilog code of MUX, DEMUX, Adder, Subtractor, Encoder, Decoder, FlipFlops, Registers and counters

Language: Verilog - Size: 8.97 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

mircea-pavel-anton/VHDL-Decryption 📦

A small decryption module, written in Verilog, as a university assignment.

Language: Verilog - Size: 557 KB - Last synced at: 2 days ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0

melchisedech333/verilog-experiments

:space_invader: My studies with Verilog and notions of digital systems.

Language: Verilog - Size: 391 KB - Last synced at: 3 months ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

oriod-malo/My-Custom-CPU-ISA-Assembly

A small CPU / ISA and a testbench that displays its instructions' equivalent in assembly&machine language.

Language: Verilog - Size: 150 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

KarlJoad/ece497

ECE 497 - Special Project Research

Language: TeX - Size: 49 MB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 1

vasanthkumar18/Cache-Compression

Cache compression using BASE-DELTA-IMMEDIATE process in verilog

Language: Verilog - Size: 135 KB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 10 - Forks: 6

namu00/most_used_modules

most used verilog modules

Language: Verilog - Size: 14.6 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

JAYRAM711/HDL-BITS

This Repo consists codes for some the problem statements from the HDL BITS website and can help you in your journey to learn Verilog from the scratch

Size: 519 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

josephkb87/VerilogBasics

Basics of Verilog implementation

Language: SystemVerilog - Size: 19.5 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

aklsh/getting-started-with-verilog

Verilog modules for beginners

Language: Verilog - Size: 44.9 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 18 - Forks: 9

msarmad900/Verilog-Codes

Verilog

Size: 4.88 MB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

mihir8181/VerilogHDL-Codes

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

Language: Verilog - Size: 3.45 MB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 21 - Forks: 3

skynatepro/MIPS32

Design of 32-bit MIPS Processor

Language: Verilog - Size: 5.7 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 0

MSaaad/vlsi-lab-tasks

Codes performed in labs using Xilinx ISE 14.7

Language: Verilog - Size: 378 KB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

MuballighHossain/CMOS_3_To_8_Decoder_VLSI

Language: Verilog - Size: 32.2 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

anonsachin/verilog-generator

A generator tool which creates verilog modules like, greycode encoder and decoders.

Size: 1000 Bytes - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

sts08015/HDLBits_solution

My own HDLBits solution :)

Language: Verilog - Size: 77.1 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0

mohanadtalat91/Verilog-HDL

A Verilog HDL code

Language: Verilog - Size: 16.6 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

fabiano77/MU0_project

This project is to design a processor and memory in the digital system design course at university.

Language: Verilog - Size: 1.74 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

ukashasohail/MIPS_32bit_SCDP_Verilog

An implementation of 32-bits MIPS Single Cycle Datapath in Verilog HDL.

Language: Verilog - Size: 14.6 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

Saraja98/Photonics-interconnects-for-Clock-routing

Size: 5.86 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

pritindra/Verilog_codes

My ongoing practice verilog hdl codes.

Language: Verilog - Size: 6.64 MB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

zeeshan0309/pseudo_random_sequence_generator

Language: SystemVerilog - Size: 3.91 KB - Last synced at: 10 months ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

abdallahabusidu/CMP305-introduction-Verilog

introduction to Verilog in Integrated Circuit Design And VLSI technology

Language: Verilog - Size: 5.86 KB - Last synced at: 3 months ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

franklinthony/food-machine

Projeto de uma máquina de lanche desenvolvido como atividade final da disciplina Circuitos Lógicos II.

Language: Verilog - Size: 33.2 KB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 2

jayaramanrp/system-verilog

simple system verilog files

Language: SystemVerilog - Size: 6.84 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0