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GitHub topics: controlpath

shahed22/Architectural-Design-for-Bus-interface-connected-with-LFSR

bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications

Language: Verilog - Size: 208 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

ARohithReddy/multiplier

Digital circuit description to perform multiplication with data_path and control_path using verilog

Language: Verilog - Size: 155 KB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 1

vipul43/RISC_V_architecture_design

designing RISC-V architecture using Verilog HDL in XILINX VIVADO PC SUITE

Language: Verilog - Size: 2.15 MB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 0

Related Keywords
controlpath 3 datapath 3 verilog 2 xilinx-vivado 1 verilog-hdl 1 riscv64 1 risc-varchitecture 1 hennessy-and-patterson 1 verilog-code 1 multiplier 1 data-path 1 testbench 1 soc 1 rtl 1 peripherals 1 lfsr-algorithm 1 lfsr 1 interface 1 fsm 1 datapath-design 1 bus-interface 1 asic-design 1 asic 1 architecture 1 32bit 1 32-bit 1