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GitHub topics: verilog-simulator

galihru/logicsim

The Logic Simulator is an advanced tool designed to facilitate the understanding of sequential circuit design. This application implements fundamental concepts of computer architecture and digital systems engineering through an intuitive drag-and-drop interface, providin

Language: JavaScript - Size: 270 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

verilator/verilator

Verilator open-source SystemVerilog simulator and lint system

Language: C++ - Size: 61.4 MB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 3,006 - Forks: 684

f4pga/f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Language: Jupyter Notebook - Size: 9.52 MB - Last synced at: 11 days ago - Pushed at: 12 days ago - Stars: 292 - Forks: 114

jElhamm/Verilog-HDL-Codes-Collection

"Repository containing a collection of Verilog code modules and test bench for digital design projects. "

Language: Verilog - Size: 387 KB - Last synced at: 7 days ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

JeffDeCola/my-verilog-examples

A place to keep my synthesizable verilog examples.

Language: Verilog - Size: 13.7 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 36 - Forks: 11

Rudra-Joshi-002/Verilog_Codes

This Repository shows the implementation and results of various codes that I write in Verilog HDL

Language: Verilog - Size: 19.2 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

wasifijaz/Digital-System-Design-Verilog-Implementation

Digital System Design Verilog Implementation

Language: Verilog - Size: 48.8 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

Arjun-Narula/Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

Language: JavaScript - Size: 2.07 MB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 29 - Forks: 7

vb000/vcs-slave-mode

Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).

Language: Makefile - Size: 1.95 KB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 1

neelkshah/MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

Language: Verilog - Size: 138 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 64 - Forks: 13

mateuspinto/FPGA_Verilog_Ballot_Box-TP2-ISL-UFV

Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.

Language: Verilog - Size: 10.1 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 4 - Forks: 1

AUCOHL/Classic-Playground 📦

A playground based on the classic version of the Cloud V IDE

Language: JavaScript - Size: 3.96 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 1

ali-asnaashari/Computer_Architecture_Lab-CAL-2021

Computer Architecture Lab Course 2022/1400, Fall CSE & IT Dept., Shiraz University

Language: Verilog - Size: 1.2 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 4 - Forks: 0

Bhargav-962/4-bit_Register-Verilog

A verilog program that mimics the circuitry of a 4-bit register implemented with four 4x1 multiplexers and four D-Flipflops

Language: Verilog - Size: 4.88 KB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 1

cw1997/verilog-parser

Verilog HDL Parser

Language: ANTLR - Size: 38.1 KB - Last synced at: 8 days ago - Pushed at: about 4 years ago - Stars: 4 - Forks: 0

gokcedemir/Mips-processor

32-bit MIPS processor fully supporting all core instructions

Language: Verilog - Size: 1.87 MB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 0 - Forks: 0