GitHub topics: verilog-simulations
f4pga/f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Language: Jupyter Notebook - Size: 9.52 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 295 - Forks: 115
yomnahisham/ts-verilog-simulator
A web-based Verilog simulator for designing, running, and visualizing RTL code in-browser.
Language: TypeScript - Size: 292 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 6 - Forks: 0