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GitHub / JeffDeCola / my-verilog-examples
A place to keep my synthesizable verilog examples.
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/JeffDeCola%2Fmy-verilog-examples
Stars: 27
Forks: 9
Open Issues: 0
License: mit
Language: Verilog
Repo Size: 13.1 MB
Dependencies:
0
Created: over 5 years ago
Updated: 3 months ago
Last pushed: 11 months ago
Last synced: 3 months ago
Topics: asic, asic-design, fpga, gtkwave, hardware, hardware-architecture, hardware-description-language, hdl, iverilog, simulator, synthesis, synthesize, systemverilog, verilog, verilog-simulator, vivado, waveform, xilinx
Files
No dependencies found