GitHub / JeffDeCola / my-verilog-examples
A place to keep my synthesizable verilog examples.
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/JeffDeCola%2Fmy-verilog-examples
Stars: 36
Forks: 11
Open issues: 0
License: mit
Language: Verilog
Size: 13.7 MB
Dependencies parsed at: Pending
Created at: about 6 years ago
Updated at: 10 days ago
Pushed at: 10 days ago
Last synced at: 10 days ago
Topics: asic, asic-design, fpga, gtkwave, hardware, hardware-architecture, hardware-description-language, hdl, iverilog, simulator, synthesis, synthesize, systemverilog, verilog, verilog-simulator, vivado, waveform, xilinx
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