Ecosyste.ms: Repos
An open API service providing repository metadata for many open source software ecosystems.
GitHub topics: verilog-components
ZipCPU/sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
Language: Verilog - Size: 7.1 MB - Last synced: 4 days ago - Pushed: 4 days ago - Stars: 146 - Forks: 25
ultraembedded/cores
Various HDL (Verilog) IP Cores
Language: Verilog - Size: 211 KB - Last synced: 25 days ago - Pushed: almost 3 years ago - Stars: 637 - Forks: 196
ZipCPU/dblclockfft
A configurable C++ generator of pipelined Verilog FFT cores
Language: C++ - Size: 1.08 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 204 - Forks: 28
Johnlon/spam-1
Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu
Language: Verilog - Size: 204 MB - Last synced: 2 months ago - Pushed: 9 months ago - Stars: 60 - Forks: 8
TimRudy/ice-chips-verilog
IceChips is a library of all common discrete logic devices in Verilog
Language: Verilog - Size: 1.41 MB - Last synced: about 1 month ago - Pushed: 3 months ago - Stars: 117 - Forks: 18
EhsanShahbazii/Digital-VLSI-System-Design-Projects
سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر
Language: Verilog - Size: 73.2 KB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 2 - Forks: 0
Jamesits/verilog-basic-blocks
数电作业
Language: Verilog - Size: 120 KB - Last synced: about 1 month ago - Pushed: over 6 years ago - Stars: 2 - Forks: 1
wyvernSemi/mem_model
High speed C/C++ based behavioural Verilog memory model
Language: C - Size: 1.07 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 4 - Forks: 0
ferhatozkan/Digital-Logic-Design-Project
University of Marmara, CSE3015 2018 Fall Project
Language: Java - Size: 2.6 MB - Last synced: 11 months ago - Pushed: about 5 years ago - Stars: 2 - Forks: 0
fightforit/SystemVerilog-Design-Blocks-Common-Use-Cases-and-Examples
Language: SystemVerilog - Size: 20.5 KB - Last synced: 12 months ago - Pushed: 12 months ago - Stars: 0 - Forks: 0
TimRudy/uart-verilog
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
Language: Verilog - Size: 26.7 MB - Last synced: 12 months ago - Pushed: 12 months ago - Stars: 1 - Forks: 0
WualFabre/FPGA-Verilog
Practices related to the fundamental level of the programming language Verilog.
Language: Verilog - Size: 5.35 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 10 - Forks: 1
adibis/Interrupt_Controller
An 8 input interrupt controller written in Verilog.
Language: Verilog - Size: 112 KB - Last synced: about 1 year ago - Pushed: about 12 years ago - Stars: 12 - Forks: 9
BrianHGinc/Verilog-Floating-Point-Clock-Divider
Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.
Language: Verilog - Size: 273 KB - Last synced: about 1 year ago - Pushed: almost 2 years ago - Stars: 8 - Forks: 1
josephkb87/VerilogBasics
Basics of Verilog implementation
Language: SystemVerilog - Size: 19.5 KB - Last synced: about 1 year ago - Pushed: almost 2 years ago - Stars: 1 - Forks: 0
neelkshah/MIPS-Processor
5-stage pipelined 32-bit MIPS microprocessor in Verilog
Language: Verilog - Size: 138 KB - Last synced: about 1 year ago - Pushed: about 4 years ago - Stars: 64 - Forks: 13
mohanadtalat91/Verilog-HDL
A Verilog HDL code
Language: Verilog - Size: 16.6 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0
ZipCPU/wbfmtx
A wishbone controlled FM transmitter hack
Language: Verilog - Size: 197 KB - Last synced: about 1 year ago - Pushed: over 4 years ago - Stars: 19 - Forks: 1
kivyfreakt/interfaces
Реализация распространенных интерфейсов
Language: Verilog - Size: 5.84 MB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0
Wissance/QuickSPI
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
Language: Verilog - Size: 127 KB - Last synced: about 1 year ago - Pushed: over 6 years ago - Stars: 14 - Forks: 3
IzyaSoft/EasyHDLLib
A coocbook of HDL (primarily Verilog) modules
Language: Verilog - Size: 315 KB - Last synced: about 1 year ago - Pushed: about 7 years ago - Stars: 5 - Forks: 0
yvesemmanuel/introduction_verilog
digital systems
Language: Verilog - Size: 202 KB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 0 - Forks: 0
yvesemmanuel/microwave
second project - Digital System
Language: Verilog - Size: 4.21 MB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 0 - Forks: 1
verilogcodesarchive/verilogutils
Language: Verilog - Size: 74.2 KB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 0 - Forks: 0
InvincibleJuggernaut/Synthesis
A collection of digital circuits using Verilog.
Language: Verilog - Size: 29.3 KB - Last synced: about 1 year ago - Pushed: almost 3 years ago - Stars: 0 - Forks: 0
NotZombieFood/VerilogModules
Verilog modules for reference
Language: C - Size: 9.91 MB - Last synced: about 1 year ago - Pushed: over 6 years ago - Stars: 1 - Forks: 0
