GitHub topics: synopsys-vcs
cong2738/May_team_project_I2C_SPI
i2c com, spi com with AMBA AXI
Language: VHDL - Size: 71.5 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 0 - Forks: 3

OpenEDF/verilog-basic
learn the combinational and sequential logic circuit.
Language: SystemVerilog - Size: 24.3 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 15 - Forks: 1

vb000/vcs-slave-mode
Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).
Language: Makefile - Size: 1.95 KB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 1
