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GitHub topics: synopsys-vcs

OpenEDF/verilog-basic

learn the combinational and sequential logic circuit.

Language: SystemVerilog - Size: 24.3 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 15 - Forks: 1

vb000/vcs-slave-mode

Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).

Language: Makefile - Size: 1.95 KB - Last synced at: over 1 year ago - Pushed at: about 5 years ago - Stars: 4 - Forks: 1

Related Keywords
synopsys-vcs 2 fpga 1 fpga-programming 1 ice40up5k 1 iverilog 1 simulation 1 simulator 1 synopsys-dc 1 verilog 1 vhdl 1 shared-object 1 verilog-simulator 1