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GitHub topics: synopsys-vcs

OpenEDF/verilog-basic

learn the combinational and sequential logic circuit.

Language: SystemVerilog - Size: 24.3 MB - Last synced at: about 11 hours ago - Pushed at: about 12 hours ago - Stars: 15 - Forks: 1

cong2738/May_team_project_I2C_SPI

i2c com, spi com with AMBA AXI

Language: VHDL - Size: 71.5 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 0 - Forks: 3

vb000/vcs-slave-mode

Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).

Language: Makefile - Size: 1.95 KB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 1

Related Keywords
synopsys-vcs 3 fpga 2 verilog 2 verilog-simulator 1 shared-object 1 vivado 1 verdi 1 systemverilog 1 spi 1 microblaze 1 i2c 1 hardware-description-language 1 c 1 basys3-fpga 1 axi 1 vhdl 1 synopsys-dc 1 simulator 1 simulation 1 iverilog 1 ice40up5k 1 fpga-programming 1