GitHub / OpenEDF / verilog-basic
learn the combinational and sequential logic circuit.
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/OpenEDF%2Fverilog-basic
PURL: pkg:github/OpenEDF/verilog-basic
Stars: 15
Forks: 1
Open issues: 0
License: gpl-3.0
Language: SystemVerilog
Size: 24.3 MB
Dependencies parsed at: Pending
Created at: almost 4 years ago
Updated at: 7 days ago
Pushed at: 7 days ago
Last synced at: 7 days ago
Topics: fpga, fpga-programming, ice40up5k, iverilog, simulation, simulator, synopsys-dc, synopsys-vcs, verilog, vhdl
Loading...