GitHub / mircea-pavel-anton / VHDL-Decryption
A small decryption module, written in Verilog, as a university assignment.
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/mircea-pavel-anton%2FVHDL-Decryption
PURL: pkg:github/mircea-pavel-anton/VHDL-Decryption
Stars: 3
Forks: 0
Open issues: 0
License: gpl-3.0
Language: Verilog
Size: 557 KB
Dependencies parsed at: Pending
Created at: over 4 years ago
Updated at: over 2 years ago
Pushed at: over 4 years ago
Last synced at: 5 days ago
Topics: caesar-cipher, caesar-cipher-algorithm, decryption, fence-cipher, scytale-cipher, verilog, verilog-code, verilog-hdl, verilog-project, zigzag-cipher
Funding Links https://github.com/sponsors/mircea-pavel-anton