robseb/rsyocto

🤖 SoCFPGA: Open-Source Embedded Linux Distribution with a highly flexible build system, developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)

Language: Python - Size: 119 MB - Last synced at: 7 days ago - Pushed at: over 3 years ago - Stars: 105 - Forks: 26

shrine-maiden-heavy-industries/torii-boards

Torii HDL Board Definitions

Language: Python - Size: 55 MB - Last synced at: 27 days ago - Pushed at: 27 days ago - Stars: 0 - Forks: 0

BakxY/VHDL-QQS

VS Code extension for Intel Quartus: seamless project compilation, direct access to the Quartus programmer and RTL viewer, automated testbench generation for QuestaSim, integrated QuestaSim simulation, streamlined project configuration, direct file management, top-level entity changes, and on-demand source file formatting.

Language: TypeScript - Size: 806 KB - Last synced at: 28 days ago - Pushed at: 28 days ago - Stars: 0 - Forks: 0

robseb/HPS2FPGAmapping

SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)

Language: Verilog - Size: 11 MB - Last synced at: 7 days ago - Pushed at: almost 4 years ago - Stars: 37 - Forks: 13

robseb/Django2FPGAdemo

Demonstration how to build a Management Web interface to interact with the FPGA fabric and change the FPGA configuration with the Django Framework

Language: Python - Size: 2.38 MB - Last synced at: 7 days ago - Pushed at: almost 4 years ago - Stars: 12 - Forks: 5

spcl/hls_tutorial_examples

Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".

Language: C++ - Size: 1.27 MB - Last synced at: 14 days ago - Pushed at: over 3 years ago - Stars: 199 - Forks: 46

anthony-bernaert/ftdi-jtag-programmer

FTDI-based JTAG Programmer for FPGAs

Size: 554 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 6 - Forks: 4

spcl/stencilflow

Language: Python - Size: 30.5 MB - Last synced at: 14 days ago - Pushed at: over 3 years ago - Stars: 16 - Forks: 3

mbtaylor1982/ReSDMAC

Verilog code to replace the Commodore SDMAC found in the A3000

Language: Verilog - Size: 160 MB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 40 - Forks: 3

robseb/socfpgaPlatformGenerator

Script to build the bootloader (u-boot) and bring all components to a bootable image for Intel (ALTERA) SoC-FPGAs

Language: Python - Size: 1.63 MB - Last synced at: 7 days ago - Pushed at: 11 months ago - Stars: 8 - Forks: 4

definelicht/hlslib

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

Language: C++ - Size: 577 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 311 - Forks: 58

AnyDSL/flower

A Comprehensive Dataflow Compiler for High-Level Synthesis

Language: CMake - Size: 3.61 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 9 - Forks: 3

robseb/meta-intelfpga

Yocto Project BSP meta-layer for Intel (ALTERA) SoC-FPGAs (SoCFPGA) - with step by step guide

Language: BitBake - Size: 600 KB - Last synced at: 12 days ago - Pushed at: 11 months ago - Stars: 21 - Forks: 8

Insper/Embarcados-Avancados

SoC and Embedded Linux

Language: JavaScript - Size: 81.3 MB - Last synced at: about 2 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 11

fm16191/fpga-streams-bandwith

Load vs Store comparison on Intel FPGA using oneAPI

Language: C++ - Size: 132 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 2

robseb/NIOSII_EclipseCompProject

Automatically create a NIOS II Eclipse Project with the latest FreeRTOS Version, the Intel hwlib and more...

Language: C - Size: 5.02 MB - Last synced at: 7 days ago - Pushed at: almost 4 years ago - Stars: 6 - Forks: 3

robseb/rstoolsA10

Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Arria 10 SX SoCFPGA

Language: C++ - Size: 1.27 MB - Last synced at: 7 days ago - Pushed at: almost 4 years ago - Stars: 5 - Forks: 2

canhld94/HeteroServing

Serving object detection models on different hardware.

Language: C++ - Size: 37 MB - Last synced at: 12 months ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

abr/c5soc-ocl-id

OpenCL wrapper for Intel's unique chip ID function built for the Cyclone V chip on the DE1-SoC board

Language: C++ - Size: 354 KB - Last synced at: about 1 year ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 0

dhwanish-3/Verilog-Programming-Logic-Design-Lab

Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator

Language: Verilog - Size: 28.3 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

AnyDSL/anyhls

High-Level Synthesis with Partial Evaluation

Language: CMake - Size: 81.1 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 11 - Forks: 1

robseb/rstoolsCY5

Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Cyclone V SoCFPGA

Language: C - Size: 1.74 MB - Last synced at: 7 days ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 5

osafune/canarium_air

IntelFPGA configuration & Avalon-MM access library for FlashAir

Language: Lua - Size: 480 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 12 - Forks: 2

teratide/fletcher-opae

Fletcher Open Programmable Acceleration Engine platform support

Language: C - Size: 1.57 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 2

andrsmllr/de0_atlas_soc_devbrd

Play and learn with the Terasic DE0-Atlas/Nano-SoC Kit featuring a Altera/Intel Cyclone V 5CSEMA4U23C6N FPGA with integrated dual-core ARM Cortex-A9.

Language: Verilog - Size: 30.3 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0