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GitHub topics: synchronous-counter

EngineerMichael/ModelSim-Altera-Project-Electronics-

⎔ Using the program ModelSim-Altera, to execute a Synchronous Counter with Asynchronous and Synchronous Reset project by implementing a 2 Bit, 4 Bit, 6 Bit, and 11 Bit for counters by using VHDL code.

Size: 25.4 KB - Last synced at: about 2 months ago - Pushed at: 4 months ago - Stars: 3 - Forks: 0

levyashvin/verilog_codes

basic implementation of logic structures using verilog

Language: Verilog - Size: 17.6 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

scriptographers/CS254-Assignment-6

Assignment 6, Digital Logic Design Lab, Spring 2021, IIT Bombay

Language: VHDL - Size: 5.48 MB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

Related Keywords
synchronous-counter 3 up-down-counter 1 stg 1 fsm 1 verilog-testbenches 1 t-flipflop 1 sr-flip-flop 1 siso 1 sipo 1 sequence-detector 1 registers 1 priority-encoder 1 piso 1 pipo 1 jk-flipflop 1 half-subtractor 1 full-subtractor 1 full-adder 1 d-flipflop 1 vhdl-code 1 modelsim 1 altera-quartus 1 altera-fpga 1 altera-de1 1