ktbarrett/coconext

Staging area for new features of cocotb

Language: Python - Size: 41 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

chili-chips-ba/wireguard-fpga

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

Language: VHDL - Size: 1.91 GB - Last synced at: about 3 hours ago - Pushed at: 2 days ago - Stars: 80 - Forks: 0

Weiyet/RTLStructLib

RTL data structure

Language: SystemVerilog - Size: 247 KB - Last synced at: 6 days ago - Pushed at: 6 days ago - Stars: 1 - Forks: 0

apfaudio/eurorack-pmod

A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

Language: SystemVerilog - Size: 27.7 MB - Last synced at: 13 days ago - Pushed at: 13 days ago - Stars: 203 - Forks: 13

mmichilot/cocotb_kernel

A cocotb kernel for Jupyter

Language: Python - Size: 36.1 KB - Last synced at: 8 days ago - Pushed at: 10 months ago - Stars: 7 - Forks: 0

fvutils/pyvsc

Python packages providing a library for Verification Stimulus and Coverage

Language: Python - Size: 6.98 MB - Last synced at: 19 days ago - Pushed at: 19 days ago - Stars: 120 - Forks: 29

themperek/cocotb-vivado

Limited python / cocotb interface to Xilinx/AMD Vivado simulator.

Language: Python - Size: 36.1 KB - Last synced at: 12 days ago - Pushed at: 3 months ago - Stars: 37 - Forks: 6

0BAB1/HOLY_CORE_COURSE

Learn how to build our own RV32I core and use it on FPGA.

Language: Python - Size: 11.1 MB - Last synced at: 25 days ago - Pushed at: 25 days ago - Stars: 121 - Forks: 11

amutioalex/cocoman

Regression runner for cocotb-based verification workflows.

Language: Python - Size: 38.1 KB - Last synced at: 25 days ago - Pushed at: 25 days ago - Stars: 1 - Forks: 0

fjpolo/FPGA_Project-Creator

FPGA template project creator

Language: Shell - Size: 64.5 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

cocotb/cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Language: Python - Size: 5.9 MB - Last synced at: about 1 month ago - Pushed at: 7 months ago - Stars: 63 - Forks: 46

mciepluc/cocotb-coverage

Functional Coverage and Constrained Randomization Extensions for Cocotb

Language: Python - Size: 292 KB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 110 - Forks: 19

aignacio/cocotbext-ahb

Cocotb AHB Extension - AHB VIP

Language: Python - Size: 1.37 MB - Last synced at: 9 days ago - Pushed at: 3 months ago - Stars: 14 - Forks: 9

merledu/coco-rvtb

General testbench for RISC-V CPUs

Language: Makefile - Size: 46.9 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 4 - Forks: 7

JitheshVijay/cocotbext-qspi

Cocotb extension for QSPI verification

Language: Python - Size: 77.1 KB - Last synced at: about 1 month ago - Pushed at: 11 months ago - Stars: 3 - Forks: 2

intel/rohd-cosim

Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators

Language: Dart - Size: 745 KB - Last synced at: 21 days ago - Pushed at: 3 months ago - Stars: 23 - Forks: 4

MarcoRiggirello/CholeskyHDL

VHDL implementation of "Computing the Cholesky Factorization Using a Systolic Architecture"

Language: Python - Size: 25.4 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

psychogenic/microcotb

micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop

Language: Python - Size: 1.38 MB - Last synced at: 6 days ago - Pushed at: 2 months ago - Stars: 13 - Forks: 1

rj45/rjsc5

rjsc5 a 16-bit RISC-V CPU

Language: Assembly - Size: 1.51 MB - Last synced at: about 1 month ago - Pushed at: 4 months ago - Stars: 3 - Forks: 0

raumzeitt/rz-jenc

JPEG encoder IP core(s) written in Verilog.

Language: SystemVerilog - Size: 20.9 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 2 - Forks: 1

chuckb/ghdl-interactive-sim

Interactive GHDL simulation of a VHDL adder using Python, Cocotb, and pygame

Language: Python - Size: 252 KB - Last synced at: 30 days ago - Pushed at: over 3 years ago - Stars: 9 - Forks: 3

RDSik/verilog-transceiver

Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit

Language: Verilog - Size: 636 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 3 - Forks: 0

RDSik/si5340-config-loader

Module for load configuration from ClockBuilderPro to Si5340 PLL via i2c interface

Language: Verilog - Size: 2.15 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 1 - Forks: 1

mcejp/Poly94

Yet another faux-retro game system

Language: Verilog - Size: 1.48 MB - Last synced at: 6 days ago - Pushed at: about 1 year ago - Stars: 3 - Forks: 0

JitheshVijay/cocotbext-ospi

Cocotb extension for OSPI verification

Language: Python - Size: 261 KB - Last synced at: about 2 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

saikiranreddypv2104/NOC-Testbench-Using-Python

It is a automated testbench for NOC modules using Python.This can be used with different sizes.The test bench include various meta-heuristics like DE,PSO,GA.This bench is build using cocotb and PyUVM

Language: Verilog - Size: 7.29 MB - Last synced at: 8 months ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

pwiecha/yas_router

Yet Another Simple Router - a COCOTB verification of the Verilog RTL model example

Language: Verilog - Size: 68.4 KB - Last synced at: 5 months ago - Pushed at: almost 5 years ago - Stars: 3 - Forks: 2

angeliaplutus/ipcoredesign

Design & Verification of IP Cores and ICs, Artificial Intelligence

Language: VHDL - Size: 19.1 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 2

m47812/CocoTb_Example

This repository contains a simple demo used in a presentation of mine giving a beginner's guide to using CocoTB. The project provides an example of how to use CocoTB for the verification of a simple 8-bit adder.

Language: Python - Size: 1.15 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

hurisson/pyuvm_primer

Examples for using pyuvm

Language: Python - Size: 52.7 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 9 - Forks: 2

andreaskuster/black-parrot-branch-predictor

Branch Predictor Optimization for BlackParrot

Language: HTML - Size: 220 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 13 - Forks: 8

vacagonzalo/soc-workflow-vhdl

Example workflow project for VHDL development.

Language: VHDL - Size: 12.7 KB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

teobiton/cryptopen

Library of hardware accelerators for popular cryptographic hash functions in SystemVerilog

Language: Python - Size: 1.74 MB - Last synced at: 9 months ago - Pushed at: about 1 year ago - Stars: 4 - Forks: 0

npatsiatzis/recirculation_mux

Language: Python - Size: 10.6 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

npatsiatzis/fifo_asynchronous

Language: Python - Size: 7.09 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

npatsiatzis/fir

Language: Python - Size: 69.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

npatsiatzis/moving_average

Language: Python - Size: 53.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

npatsiatzis/fizzbuzz

Language: Python - Size: 10.8 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

npatsiatzis/uart

Language: VHDL - Size: 12.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

npatsiatzis/fifo_synchronous

Language: C++ - Size: 77.1 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

npatsiatzis/simple_adder

Language: Python - Size: 17.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

2uger/uart

Language: Verilog - Size: 2.31 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

npatsiatzis/barrel_shifter

Language: C++ - Size: 7.39 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

npatsiatzis/cdc_handshake

Language: Python - Size: 7.14 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Elphel/oc_jpegencode_vdt

mirror of https://git.elphel.com/Elphel/oc_jpegencode_vdt

Language: HTML - Size: 2.8 MB - Last synced at: over 1 year ago - Pushed at: almost 9 years ago - Stars: 0 - Forks: 0

npatsiatzis/VGA

Language: SystemVerilog - Size: 4.46 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

npatsiatzis/gray_bin_conv

Language: Python - Size: 46.9 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

npatsiatzis/bcd_bin_conv

Language: Python - Size: 55.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

EngCake/icarus-verilog

Quick starter project for using Icarus Verilog + Cocotb

Language: Python - Size: 3.91 KB - Last synced at: 11 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

yasin-peker/Verilog-HDL-Based-Car-Parking-System-FPGA

This repository contains the Verilog HDL implementation of a Car Parking System running on an FPGA. The system is designed to manage car entry and exit through two sensors located at the entrance and exit of the car park. It allows registered users to enter the car park by entering their passwords and controls the traffic lights accordingly.

Language: Python - Size: 7.59 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

ttchisholm/10g-low-latency-ethernet

10G Low Latency Ethernet

Language: SystemVerilog - Size: 529 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 12 - Forks: 2

Elphel/vdt-plugin

mirror of https://git.elphel.com/Elphel/vdt-plugin

Language: Java - Size: 3.39 MB - Last synced at: 5 months ago - Pushed at: over 7 years ago - Stars: 15 - Forks: 1

167rgc911/hdl_study

mostly simple VHDL stuff

Size: 110 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

puneeth714/parity_calc

parity calculator for the given bit stream

Language: Python - Size: 242 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

xiajenny/missing-module-cocotb-example

Simulate incomplete verilog module with python

Language: Python - Size: 2.93 KB - Last synced at: almost 2 years ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 0

rafaelnp/fpga_dev_docker

Docker image for fpga development

Language: Dockerfile - Size: 9.77 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0