hurisson/pyuvm_primer

Examples for using pyuvm

Language: Python - Size: 52.7 KB - Last synced: 1 day ago - Pushed: 1 day ago - Stars: 9 - Forks: 2

RDSik/i2c_master

Language: Verilog - Size: 41 KB - Last synced: 3 days ago - Pushed: 3 days ago - Stars: 0 - Forks: 0

apfelaudio/eurorack-pmod

A eurorack-friendly audio frontend compatible with many FPGA boards.

Language: SystemVerilog - Size: 20.8 MB - Last synced: 15 days ago - Pushed: 15 days ago - Stars: 162 - Forks: 8

teobiton/cryptopen

Library of hardware accelerators for popular cryptographic hash functions in SystemVerilog

Language: Python - Size: 1.74 MB - Last synced: 20 days ago - Pushed: 4 months ago - Stars: 4 - Forks: 0

mciepluc/cocotb-coverage

Functional Coverage and Constrained Randomization Extensions for Cocotb

Language: Python - Size: 292 KB - Last synced: 2 days ago - Pushed: 7 months ago - Stars: 101 - Forks: 14

fvutils/pyvsc

Python packages providing a library for Verification Stimulus and Coverage

Language: Python - Size: 4.9 MB - Last synced: 4 days ago - Pushed: about 2 months ago - Stars: 105 - Forks: 24

saikiranreddypv2104/NOC-Testbench-Using-Python

It is a automated testbench for NOC modules using Python.This can be used with different sizes.The test bench include various meta-heuristics like DE,PSO,GA.This bench is build using cocotb and PyUVM

Language: Verilog - Size: 7.29 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 1 - Forks: 0

cocotb/cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Language: Python - Size: 5.85 MB - Last synced: about 1 month ago - Pushed: 3 months ago - Stars: 46 - Forks: 33

aignacio/cocotbext-ahb

Cocotb AHB Extension - AHB VIP

Language: Python - Size: 1.21 MB - Last synced: 9 days ago - Pushed: 5 months ago - Stars: 7 - Forks: 4

RDSik/FPGA-transceiver

Language: Verilog - Size: 400 KB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 0 - Forks: 0

intel/rohd-cosim

Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators

Language: Dart - Size: 650 KB - Last synced: about 2 months ago - Pushed: 3 months ago - Stars: 14 - Forks: 3

andreaskuster/black-parrot-branch-predictor

Branch Predictor Optimization for BlackParrot

Language: HTML - Size: 220 MB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 13 - Forks: 8

vacagonzalo/soc-workflow-vhdl

Example workflow project for VHDL development.

Language: VHDL - Size: 12.7 KB - Last synced: 3 months ago - Pushed: over 1 year ago - Stars: 1 - Forks: 0

themperek/cocotb-vivado

Limited python / cocotb interface to Xilinx Vivado XSIM simulator.

Language: Python - Size: 30.3 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 14 - Forks: 1

Elphel/vdt-plugin

mirror of https://git.elphel.com/Elphel/vdt-plugin

Language: Java - Size: 3.39 MB - Last synced: 3 months ago - Pushed: over 6 years ago - Stars: 15 - Forks: 1

mcejp/Poly94

Yet another faux-retro game system

Language: Verilog - Size: 1.48 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 2 - Forks: 0

angeliaplutus/ipcoredesign

Design & Verification of IP Cores and ICs, Artificial Intelligence

Language: VHDL - Size: 18.4 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 1 - Forks: 1

pwiecha/yas_router

Yet Another Simple Router - a COCOTB verification of the Verilog RTL model example

Language: Verilog - Size: 68.4 KB - Last synced: 4 months ago - Pushed: almost 4 years ago - Stars: 2 - Forks: 2

npatsiatzis/recirculation_mux

Language: Python - Size: 10.6 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

npatsiatzis/fifo_asynchronous

Language: Python - Size: 7.09 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

npatsiatzis/fir

Language: Python - Size: 69.3 KB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

npatsiatzis/moving_average

Language: Python - Size: 53.7 KB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

npatsiatzis/fizzbuzz

Language: Python - Size: 10.8 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

npatsiatzis/uart

Language: VHDL - Size: 12.7 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

npatsiatzis/fifo_synchronous

Language: C++ - Size: 77.1 KB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 0 - Forks: 0

npatsiatzis/simple_adder

Language: Python - Size: 17.7 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

2uger/uart

Language: Verilog - Size: 2.31 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

npatsiatzis/barrel_shifter

Language: C++ - Size: 7.39 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

npatsiatzis/cdc_handshake

Language: Python - Size: 7.14 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

Elphel/oc_jpegencode_vdt

mirror of https://git.elphel.com/Elphel/oc_jpegencode_vdt

Language: HTML - Size: 2.8 MB - Last synced: 10 months ago - Pushed: almost 8 years ago - Stars: 0 - Forks: 0

npatsiatzis/VGA

Language: SystemVerilog - Size: 4.46 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

npatsiatzis/gray_bin_conv

Language: Python - Size: 46.9 KB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

npatsiatzis/bcd_bin_conv

Language: Python - Size: 55.7 KB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0

rj45/rjsc5

rjsc5 a 16-bit RISC-V CPU

Language: Assembly - Size: 1.46 MB - Last synced: 10 months ago - Pushed: over 1 year ago - Stars: 2 - Forks: 0

EngCake/icarus-verilog

Quick starter project for using Icarus Verilog + Cocotb

Language: Python - Size: 3.91 KB - Last synced: 3 days ago - Pushed: 10 months ago - Stars: 0 - Forks: 0

yasin-peker/Verilog-HDL-Based-Car-Parking-System-FPGA

This repository contains the Verilog HDL implementation of a Car Parking System running on an FPGA. The system is designed to manage car entry and exit through two sensors located at the entrance and exit of the car park. It allows registered users to enter the car park by entering their passwords and controls the traffic lights accordingly.

Language: Python - Size: 7.59 MB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 1 - Forks: 0

ttchisholm/10g-low-latency-ethernet

10G Low Latency Ethernet

Language: SystemVerilog - Size: 529 KB - Last synced: 11 months ago - Pushed: 11 months ago - Stars: 12 - Forks: 2

chuckb/ghdl-interactive-sim

Interactive GHDL simulation of a VHDL adder using Python, Cocotb, and pygame

Language: Python - Size: 252 KB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 3 - Forks: 1

167rgc911/hdl_study

mostly simple VHDL stuff

Size: 110 KB - Last synced: about 1 year ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

puneeth714/parity_calc

parity calculator for the given bit stream

Language: Python - Size: 242 KB - Last synced: over 1 year ago - Pushed: almost 2 years ago - Stars: 0 - Forks: 0

xiajenny/missing-module-cocotb-example

Simulate incomplete verilog module with python

Language: Python - Size: 2.93 KB - Last synced: about 1 year ago - Pushed: about 5 years ago - Stars: 1 - Forks: 0

rafaelnp/fpga_dev_docker

Docker image for fpga development

Language: Dockerfile - Size: 9.77 KB - Last synced: about 1 year ago - Pushed: over 2 years ago - Stars: 2 - Forks: 0