GitHub topics: functional-coverage
fvutils/pyvsc
Python packages providing a library for Verification Stimulus and Coverage
Language: Python - Size: 6.98 MB - Last synced at: 14 days ago - Pushed at: 14 days ago - Stars: 120 - Forks: 29
chiselverify/chiselverify
A dynamic verification library for Chisel.
Language: Scala - Size: 5.12 MB - Last synced at: 11 days ago - Pushed at: 6 months ago - Stars: 148 - Forks: 23
fvutils/pyucis
Python API to Unified Coverage Interoperability Standard (UCIS) Data
Language: Python - Size: 5.59 MB - Last synced at: 5 days ago - Pushed at: 2 months ago - Stars: 24 - Forks: 12
tmeissner/psl_with_ghdl
Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
Language: VHDL - Size: 92.8 KB - Last synced at: 8 days ago - Pushed at: 3 months ago - Stars: 66 - Forks: 5
Yashas2801/UART-Verification-using-UVM
UART verification using UVM with functional coverage, scoreboard, and test scenarios, simulated on QuestaSim.
Language: Verilog - Size: 3.04 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 3 - Forks: 0
Noamv7/Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
Language: Verilog - Size: 30.2 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0
mjhborja/functional_coverage_sv
Let's learn SystemVerilog functional coverage using the covergroup construct!
Language: SystemVerilog - Size: 27.3 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
