GitHub topics: systolic-arrays
rejunity/tiny-asic-1_58bit-matrix-mul
Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit
Language: Verilog - Size: 9.15 MB - Last synced at: 9 days ago - Pushed at: about 1 year ago - Stars: 156 - Forks: 9
alex-mckenna/clash-systolic
Systolic Networks in Clash
Language: Haskell - Size: 26.4 KB - Last synced at: 20 days ago - Pushed at: 7 months ago - Stars: 7 - Forks: 2
mohit-yadav-21/ES204_Final_Project
Final project for Digital Systems, IITGN Spring '25
Language: Verilog - Size: 720 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
UCLA-VAST/AutoSA
AutoSA: Polyhedral-Based Systolic Array Compiler
Language: C++ - Size: 34.8 MB - Last synced at: 3 months ago - Pushed at: over 2 years ago - Stars: 218 - Forks: 33
Awrsha/FPGA-Programming
Advanced FPGA implementations of cutting-edge deep learning models, optimized for high performance and energy efficiency.
Language: VHDL - Size: 113 KB - Last synced at: 3 months ago - Pushed at: 7 months ago - Stars: 1 - Forks: 0
jiaaom/HPDLA
Systolic-array based Deep Learning Accelerator generator
Language: Verilog - Size: 32.2 KB - Last synced at: 4 months ago - Pushed at: over 4 years ago - Stars: 25 - Forks: 5
aliemo/transfomers-silicon-research
Research and Materials on Hardware implementation of Transformer Model
Language: Jupyter Notebook - Size: 1.84 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 183 - Forks: 25
Noamv7/Matrix-Multiplication-Using-Systolic-Arrays-Chip-Design-and-Verification
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
Language: Verilog - Size: 30.2 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0
IntelLabs/t2sp 📦
Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)
Language: C++ - Size: 36 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 29 - Forks: 12
horizon-research/systolic-array-dataflow-optimizer
A general framework for optimizing DNN dataflow on systolic array
Language: Python - Size: 61.5 KB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 29 - Forks: 9
EMITLabGit/PsuedoSim
Analytical modeling tool for CNNs running on array-based accelerators.
Language: Python - Size: 133 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
dsa-shua/FPGA-SystolicArray
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
Language: SystemVerilog - Size: 1.59 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
joulook/Parallel-Processing-Spring-2021
In this repository you can find all of my projects for Parallel Processing Course when I was in 2nd semester of my master's at SUT.
Language: Java - Size: 3.27 MB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 0
jasonlin316/Systolic-Array-for-Smith-Waterman
This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times faster than a software running the same algorithm.
Language: Verilog - Size: 12.4 MB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 16 - Forks: 6
ic-lab-duth/FusedGCN4HLS
Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis
Language: C++ - Size: 14.9 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 11 - Forks: 1
diwu1990/uSystolic-Sim
A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
Language: C++ - Size: 9.64 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 31 - Forks: 9
NeuroFan/SystolicArray
SPICE and Behavioral simulation of systolic array equipped with error detection ABFT
Language: SourcePawn - Size: 13.2 MB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
RayWright27/SystemC-CNN-test-model
This is an unfinished test model of CNN, based on cnn.h5 Keras pretrained model EN10/KerasMNIST@4ef71d6/cnn.h5 .
Language: Jupyter Notebook - Size: 8.83 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0
gultai4ukr/PySAGS
Systolic arrays graphical simulator (SAGS), written in Python.
Language: Python - Size: 9.77 KB - Last synced at: over 2 years ago - Pushed at: about 7 years ago - Stars: 5 - Forks: 1
YuFengUofR/dataflow_optimizer
A general framework for optimizing DNN dataflow on systolic array
Language: Python - Size: 182 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 0
sebyss/Visual-representation-of-systolic-arrays
Visual representation of how systolic arrays made in Unity3d. (Just code)
Language: C# - Size: 3.91 KB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 0 - Forks: 0
