GitHub / mohit-yadav-21 / ES204_Final_Project

Final project for Digital Systems, IITGN Spring '25

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PURL: pkg:github/mohit-yadav-21/ES204_Final_Project

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License: mit
Language: Verilog
Size: 720 KB
Dependencies parsed at: Pending

Created at: 3 months ago
Updated at: 3 months ago
Pushed at: 3 months ago
Last synced at: 3 months ago

Topics: matrix-multiplication, systolic-arrays, uart-protocol, verilog-project

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