GitHub topics: hdlmake
hdl-util/hdmi
Send video/audio over HDMI on an FPGA
Language: SystemVerilog - Size: 4.13 MB - Last synced at: 5 days ago - Pushed at: over 1 year ago - Stars: 1,166 - Forks: 127
RDSik/verilog-transceiver
Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit
Language: Verilog - Size: 636 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 3 - Forks: 0
RDSik/si5340-config-loader
Module for load configuration from ClockBuilderPro to Si5340 PLL via i2c interface
Language: Verilog - Size: 2.15 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 1
JochiSt/Nexys4-liteeth
use the liteeth core on the Nexys4 board without SoC
Language: Tcl - Size: 71.3 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0
tomaz-suller/PoliLEG
Simplified, monocycle version of the LEGv8 processor designed by PCS Poli-USP and implemented in VHDL for Digital Systems II
Language: VHDL - Size: 182 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 1
kkrizka/endeavour_firmware
Testbench for playing with the Endeavour protocol used by AMACv2.
Language: Verilog - Size: 27.3 KB - Last synced at: about 2 years ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0
tomaz-suller/hdlmake-template
Template for use with the build tool hdlmake, specifically set up for VHDL development and simulation.
Language: VHDL - Size: 4.88 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0
sameer/DE2-115-template
HDLMake template for terasIC DE2-115
Language: Tcl - Size: 8.79 KB - Last synced at: 5 days ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0
