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GitHub topics: yosys-slang

PyFPGA/HDLconv

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

Language: Python - Size: 5.15 MB - Last synced at: 10 days ago - Pushed at: 2 months ago - Stars: 24 - Forks: 2

PyFPGA/containers

Containers for FOSS tools

Language: Shell - Size: 31.3 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

Related Keywords
ghdl 2 ghdl-yosys-plugin 2 yosys 2 yosys-slang 2 systemverilog 1 verilog 1 vhdl 1 slang 1 surelog 1 sv2v 1 synlig 1 verible 1 vhd2vl 1