GitHub topics: cosimulation
miree/gvi
GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
Language: C++ - Size: 239 KB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 11 - Forks: 1
wyvernSemi/vproc
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
Language: VHDL - Size: 13.7 MB - Last synced at: 6 days ago - Pushed at: about 2 months ago - Stars: 53 - Forks: 10
intel/rohd-cosim
Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
Language: Dart - Size: 745 KB - Last synced at: 3 days ago - Pushed at: 3 months ago - Stars: 23 - Forks: 4
wyvernSemi/mem_model
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
Language: VHDL - Size: 2.71 MB - Last synced at: 21 days ago - Pushed at: 5 months ago - Stars: 22 - Forks: 3
lgiannantoni/CoSimo
CoSimo dreams of becoming a co-simulation compositor for generic simulations.
Language: Python - Size: 59.6 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0
projectchrono/fmu_tools
Set of utilities to export/import FMUs out of existing C++ code
Language: C++ - Size: 2.6 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 3 - Forks: 2
five-embeddev/riscv-gtkwave
GTKWave Decoders for RISCV
Language: C++ - Size: 463 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 7 - Forks: 0
VHDL/Compliance-Tests
Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
Language: VHDL - Size: 260 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 28 - Forks: 8
NikLeberg/vhpi_jtag
Connect to your GHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> vhpi_jtag <-VHPI-> GHDL
Language: C - Size: 37.1 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 7 - Forks: 1
tinrabuzin/PSSEComm
Enables the co-simulation between PSS/E and Matlab/Simulink
Language: C++ - Size: 260 KB - Last synced at: 10 months ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0
losfair/violet-cosim
Cosimulator for the Violet core: https://github.com/losfair/Violet
Language: Rust - Size: 8.79 KB - Last synced at: 8 days ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 0
VUnit/cosim
Interfacing VHDL and foreign languages with VUnit
Language: Python - Size: 243 KB - Last synced at: over 1 year ago - Pushed at: about 5 years ago - Stars: 14 - Forks: 2
smilies-polito/Coherence
coherence integrates evolutionary computation and co-simulation for the systematic design of protocols for cell culture and biofabrication.
Language: Python - Size: 836 MB - Last synced at: 10 days ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
GustavoAle/verilog-vpi-test
Integration test between Verilog and C++ using VPI
Language: C++ - Size: 5.86 KB - Last synced at: 5 months ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
kevinvdm/MAP_CoSim_20
CoSys MAP 2020: Integrating Physical and Virtual Objects in a Simulation Environment
Language: C - Size: 61.5 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0
