GitHub topics: hardware-verification
cyril0124/verilua
Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJIT
Language: Lua - Size: 4.53 MB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 5 - Forks: 0
ElNiak/awesome-formal-verification
Welcome to the ultimate list of resources for formal verification techniques and tools. This repository aims to provide an organized collection of high-quality resources to help professionals, researchers, and enthusiasts stay updated and advance their knowledge in the field.
Size: 24.4 KB - Last synced at: 2 days ago - Pushed at: 8 months ago - Stars: 53 - Forks: 2
cristian-mattarei/CoSA
CoreIR Symbolic Analyzer
Language: Python - Size: 7.98 MB - Last synced at: about 15 hours ago - Pushed at: almost 5 years ago - Stars: 74 - Forks: 18
rpjayaraman/DV-resource
A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
Size: 105 KB - Last synced at: 9 days ago - Pushed at: 9 days ago - Stars: 22 - Forks: 5
intel/rohd
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
Language: Dart - Size: 26.3 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 438 - Forks: 77
qiandawg/riscv-fpu-interrupt
FPGA implementation of a RISC-V RV32IMF softcore with IEEE-754 FPU and interrupt/CSR extensions, validated on Nexys A7.
Size: 2.93 KB - Last synced at: 21 days ago - Pushed at: 21 days ago - Stars: 0 - Forks: 0
pkpkp456/Learn_System_Verilog
Dive into the world of SystemVerilog with hands-on projects that bring RTL design and verification to life! From blinking counters to smart assertions, this repo is my personal sandbox for mastering the language behind modern chip design. Whether you're a VLSI enthusiast, an aspiring verification engineer, or just curious about how hardware think.
Language: Jupyter Notebook - Size: 24.1 MB - Last synced at: 25 days ago - Pushed at: 25 days ago - Stars: 0 - Forks: 0
DhruvDes/FPGA-ACC-MAC
4×4 8-bit matrix multiplication hardware accelerator using a systolic array, with a Python driver for the Basys 3 FPGA and a systolic array UVC using UVM.
Language: SystemVerilog - Size: 5.63 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0
aebeljs/VeRLPy
VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (RL). It provides a generic Gym environment implementation for building cocotb-based testbenches for verifying any hardware design.
Language: Python - Size: 108 MB - Last synced at: 22 days ago - Pushed at: almost 3 years ago - Stars: 27 - Forks: 4
mit-plv/kami
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
Language: Rocq Prover - Size: 4.2 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 155 - Forks: 27
intel/rohd-cosim
Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
Language: Dart - Size: 769 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 23 - Forks: 5
dobios/btor2-opt
Btor2 parser, circuit mitter, and code optimizer
Language: Python - Size: 140 KB - Last synced at: 2 months ago - Pushed at: 3 months ago - Stars: 10 - Forks: 4
MarleyLobao/UVM_calculator
This repository is meant for learning UVM using SystemVerilog. Through a verification environment, some hardware verification concepts are applied for a calculator with the four basic operations.
Language: SystemVerilog - Size: 137 KB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 6 - Forks: 0
intel/rohd-vf
The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.
Language: Dart - Size: 1.15 MB - Last synced at: 5 months ago - Pushed at: 8 months ago - Stars: 41 - Forks: 14
mit-plv/hemiola
A Coq framework to support structural design and proof of hardware cache-coherence protocols
Language: Coq - Size: 4.94 MB - Last synced at: 5 months ago - Pushed at: over 3 years ago - Stars: 13 - Forks: 0
jetafese/btor2mlir Fork of agurfinkel/btor2mlir
Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification
Language: C++ - Size: 1.54 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 10 - Forks: 4
manageryzy/ac_types_plus Fork of hlslibs/ac_types
Algorithmic C Datatypes
Language: C++ - Size: 12.2 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 1
supleed2/ELEC70056-HSV-CW2
About Coursework 2 for ELEC70056: Hardware and Software Verification, Hardware Component - Verification of SystemVerilog designs using assertions and timing statements
Language: SystemVerilog - Size: 3.66 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
MarleyLobao/UVM-mult-clk-domain Fork of PedroHSCavalcante/env-mult-clk-domain
Through a verification environment, this repository uses UVM to handle with multiple clock domains and virtual sequences.
Language: SystemVerilog - Size: 34.2 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
hanysalah/Design-Pattern-in-SV
This repo is created to include illustrative examples on object oriented design pattern in SV
Language: SystemVerilog - Size: 34.2 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 47 - Forks: 4
blutsvente/Specman Fork of tsvi/specman-sublime-grammar
Specman/e-language syntax for Sublime Text 3
Language: E - Size: 224 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 0
