williaml33moore/bathtub Fork of everactive/bathtub

BDD Gherkin implementation in native SystemVerilog, based on UVM.

Language: SystemVerilog - Size: 7.04 MB - Last synced: about 20 hours ago - Pushed: about 21 hours ago - Stars: 2 - Forks: 0

Pritam-Sethuraman/ALU

Language: VHDL - Size: 0 Bytes - Last synced: 14 days ago - Pushed: 14 days ago - Stars: 0 - Forks: 0

troyguo/awesome-dv

Awesome ASIC design verification

Size: 18.6 KB - Last synced: 13 days ago - Pushed: over 2 years ago - Stars: 221 - Forks: 58

wyvernSemi/vproc

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments

Language: C - Size: 7.03 MB - Last synced: about 1 month ago - Pushed: about 1 month ago - Stars: 21 - Forks: 6

abdelazeem201/Systolic-array-implementation-in-RTL-for-TPU

IC implementation of Systolic Array for TPU

Language: Verilog - Size: 17 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 90 - Forks: 20

dhruvildarji/MIPS

Made Million Instruction Per Second Processor

Size: 4.74 MB - Last synced: 4 months ago - Pushed: over 6 years ago - Stars: 3 - Forks: 1

Aperture-Electronic/Indago.NET

.NET Scripting Engine for Cadence(R) Indago(R) Interactive Verification Enviroment

Language: C# - Size: 77.1 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 3 - Forks: 0

llianmesta/NETWORKS-DRAINER

✅The most functional and the cheapest—available now with an exclusive discount on Telegram. Message us to get yours.

Size: 2.93 KB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 0

abdelazeem201/Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.

Language: Verilog - Size: 9.18 MB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 20 - Forks: 1

m-kru/go-hdl

Hdl is a tool for easing the work with hardware description languages.

Language: Go - Size: 605 KB - Last synced: 11 months ago - Pushed: over 1 year ago - Stars: 11 - Forks: 0

abdelazeem201/LEON2

The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.

Language: VHDL - Size: 816 KB - Last synced: 10 months ago - Pushed: about 1 year ago - Stars: 2 - Forks: 0

kumarrishav14/AXI

VIP for AXI Protocol

Language: SystemVerilog - Size: 80.1 KB - Last synced: about 1 year ago - Pushed: about 2 years ago - Stars: 28 - Forks: 16

Datum-Technology-Corporation/mio_demo

Moore.io Demo Project

Language: SystemVerilog - Size: 951 KB - Last synced: about 1 year ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

Lampro-Mellon/Quasar

Quasar 2.0: Chisel equivalent of SweRV-EL2

Language: Scala - Size: 155 MB - Last synced: about 1 year ago - Pushed: about 3 years ago - Stars: 23 - Forks: 8

kumarrishav14/I2C

VIP for I2C

Size: 32.2 KB - Last synced: about 1 year ago - Pushed: almost 2 years ago - Stars: 1 - Forks: 0

jpm18/VLSI-Laboratory-NIT-Rourkela

Laboraory manuals and Discussion

Language: Verilog - Size: 14.2 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 0