GitHub topics: vpi
jchabloz/verisocks
A generic verification interface to Verilog simulators using TCP sockets
Language: C - Size: 712 KB - Last synced at: 1 day ago - Pushed at: 1 day ago - Stars: 3 - Forks: 0
chipsalliance/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Language: C++ - Size: 839 MB - Last synced at: 26 days ago - Pushed at: about 1 month ago - Stars: 387 - Forks: 72
wyvernSemi/vproc
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
Language: VHDL - Size: 13.7 MB - Last synced at: 26 days ago - Pushed at: 2 months ago - Stars: 53 - Forks: 10
chuckb/ghdl-interactive-sim
Interactive GHDL simulation of a VHDL adder using Python, Cocotb, and pygame
Language: Python - Size: 252 KB - Last synced at: about 1 month ago - Pushed at: over 3 years ago - Stars: 9 - Forks: 3
semify-eda/fstdumper
Verilog VPI module to dump FST (Fast Signal Trace) databases
Language: C - Size: 313 KB - Last synced at: 20 days ago - Pushed at: over 1 year ago - Stars: 16 - Forks: 2
zhuzhzh/vpiIntro
vpi introduction thru examples
Language: C - Size: 14.6 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0
smokedevv1/politbot
Политический бот помощник для серверов дискорд.
Language: JavaScript - Size: 49.8 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
Essenceia/ethernet-physical-layer
RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
Language: Tcl - Size: 385 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 3
VUnit/cosim
Interfacing VHDL and foreign languages with VUnit
Language: Python - Size: 243 KB - Last synced at: over 1 year ago - Pushed at: about 5 years ago - Stars: 14 - Forks: 2
KamiliArsyad/orb-slam2 Fork of mateomd-dev/orb-slam2
Multi-device optimization of asynchronous ORB-SLAM2 algorithm with CUDA exploitation.
Language: C++ - Size: 41.7 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 1
icglue/stimc
a lightweight Verilog-vpi Wrapper for Stimuli Generation
Language: C - Size: 723 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0
dbhi/vboard
Virtual development board for HDL design
Language: VHDL - Size: 383 KB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 33 - Forks: 5
codenio/virtual-pi
Virtual Pi Library for mocking Raspberry Pi
Language: Python - Size: 36.1 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 4 - Forks: 6
kaushalmodi/nim-systemverilog-vpi
Using Nim to interface with Verilog and SystemVerilog test benches via VPI
Language: C - Size: 197 KB - Last synced at: about 12 hours ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 2
kaushalmodi/nim-svvpi
Wrapper for SystemVerilog VPI headers sv_vpi_user.h and vpi_user.h
Language: C - Size: 193 KB - Last synced at: about 12 hours ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
GustavoAle/verilog-vpi-test
Integration test between Verilog and C++ using VPI
Language: C++ - Size: 5.86 KB - Last synced at: 5 months ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
donn/Swiftlog
An IcarusVerilog VPI bridge for the Swift Programming Language.
Language: Swift - Size: 29.3 KB - Last synced at: about 2 months ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 0
