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GitHub / chipsalliance / Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2FSurelog

Stars: 327
Forks: 64
Open Issues: 45

License: apache-2.0
Language: C++
Repo Size: 835 MB
Dependencies: 101

Created: over 4 years ago
Updated: about 1 month ago
Last pushed: 3 months ago
Last synced: 30 days ago

Topics: antlr, antlr4-grammar, elaboration, linter, parser, parser-ast, preprocessor, python-api, systemverilog, uvm, verilog, vpi, vpi-api, vpi-standard

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