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GitHub / williaml33moore / bathtub
BDD Gherkin implementation in native SystemVerilog, based on UVM.
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/williaml33moore%2Fbathtub
Fork of everactive/bathtub
Stars: 2
Forks: 0
Open Issues: 10
License: mit
Language: SystemVerilog
Repo Size: 7.04 MB
Dependencies: pending
Created: about 1 year ago
Updated: about 2 months ago
Last pushed: about 1 month ago
Last synced: about 1 month ago
Topics: asic, asic-design, asic-verification, bdd, bdd-framework, bdd-specs, design-verification, fpga, rtl, rtl-design, soc-design, soc-verification, systemverilog, uvm, uvm-verification, verilog, verilog-hdl