GitHub topics: ahb-lite
chipsalliance/Cores-VeeR-EL2
VeeR EL2 Core
Language: SystemVerilog - Size: 898 MB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 273 - Forks: 82

chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
Language: SystemVerilog - Size: 17.6 MB - Last synced at: 12 days ago - Pushed at: almost 2 years ago - Stars: 866 - Forks: 228

shalan/MS_DMAC_AHBL
A Direct Memory Access Controller (DMAC) with AHB-lite bus interface
Language: Verilog - Size: 64.5 KB - Last synced at: about 1 month ago - Pushed at: 7 months ago - Stars: 12 - Forks: 8

shalan/MS_QSPI_XIP_CACHE
AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP
Language: Verilog - Size: 525 KB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 6

vicharak-in/vaaman-ahb-verilog
Verilog AHB Bus implementation for VAAMAN
Language: Verilog - Size: 25.4 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

TILhub/AMBA-3-AHB-Lite-Protocol
This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol
Language: C++ - Size: 327 KB - Last synced at: over 1 year ago - Pushed at: almost 7 years ago - Stars: 10 - Forks: 3

WajahatRiaz/AHB-Lite-Protocol-Verification
Attempt to develop a verification IP and plan for a bus functional model of ARM based AMBA 3 AHB-LITE Protocol. Implemented object oriented programming techniques in SysteVerilog.
Language: SystemVerilog - Size: 2.3 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 4 - Forks: 0

Lampro-Mellon/Quasar
Quasar 2.0: Chisel equivalent of SweRV-EL2
Language: Scala - Size: 155 MB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 23 - Forks: 8
