chipsalliance/Cores-VeeR-EH1

VeeR EH1 core

Language: SystemVerilog - Size: 17.6 MB - Last synced at: 4 days ago - Pushed at: almost 2 years ago - Stars: 870 - Forks: 227

chipsalliance/Cores-VeeR-EL2

VeeR EL2 Core

Language: SystemVerilog - Size: 898 MB - Last synced at: 8 days ago - Pushed at: 9 days ago - Stars: 273 - Forks: 82

chipsalliance/VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2

Language: Verilog - Size: 1.38 MB - Last synced at: 16 days ago - Pushed at: 5 months ago - Stars: 311 - Forks: 70

sifferman/fusesoc_template

Example of how to get started with olofk/fusesoc.

Language: Python - Size: 10.7 KB - Last synced at: 7 days ago - Pushed at: almost 4 years ago - Stars: 17 - Forks: 0

sifferman/fusesoc_project_template

A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.

Language: Makefile - Size: 4.88 KB - Last synced at: 7 days ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

sifferman/fpga_screensaver

This project implements the VGA protocol and allows custom images to be displayed to the screen using the Sipeed Tang Nano FPGA dev board.

Language: SystemVerilog - Size: 65.4 KB - Last synced at: 7 days ago - Pushed at: over 1 year ago - Stars: 12 - Forks: 2

sifferman/tangnano_example

Simple example of how to get started with the Tang Nano with FuseSoC.

Language: Makefile - Size: 204 KB - Last synced at: 7 days ago - Pushed at: about 3 years ago - Stars: 8 - Forks: 0

josugoar/systemverilog-template

SystemVerilog FuseSoC template

Language: SystemVerilog - Size: 7.81 KB - Last synced at: 2 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

filmil/bazel_rules_fusesoc_2

Yet another attempt at bazel rules for fusesoc. This one relies on a hermetic installation of fusesoc and edalize, and not a containerized build. See https://github.com/filmil/bazel_rules_fusesoc for that other bit.

Language: Starlark - Size: 26.4 KB - Last synced at: about 1 month ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

sifferman/find_first_set

Find first set operation in Verilog-2001 with logarithmic complexity.

Language: Verilog - Size: 90.8 KB - Last synced at: 7 days ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

midimaster21b/amba-interfaces

A few quick interfaces for AMBA standards

Language: SystemVerilog - Size: 8.79 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

dpretet/meduram

Multi-port BRAM IP for ASIC and FPGA

Language: SystemVerilog - Size: 241 KB - Last synced at: 12 months ago - Pushed at: about 4 years ago - Stars: 10 - Forks: 2

ucsbieee/mapache64

Custom 6502 Video Game Console

Language: SystemVerilog - Size: 12.7 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 9 - Forks: 1

midimaster21b/axis-video-frame-cleaner

Language: VHDL - Size: 16.6 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

midimaster21b/axis-video-greyscale

Language: VHDL - Size: 6.84 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

midimaster21b/spi-bfm

A quick SPI BFM to assist in SPI device testing and development

Language: SystemVerilog - Size: 10.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 1

m-kru/fsva

FuseSoc Verification Automation

Language: VHDL - Size: 3.73 MB - Last synced at: about 1 year ago - Pushed at: almost 3 years ago - Stars: 21 - Forks: 2

sifferman/nes_controller_interface

NES Controller Interface written in Verilog-2005

Language: Verilog - Size: 38.1 KB - Last synced at: 7 days ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

midimaster21b/uart-bfm

A quick UART BFM

Language: SystemVerilog - Size: 2.93 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 1

midimaster21b/spi-master

A simple SPI master

Language: VHDL - Size: 46.9 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 1

midimaster21b/i2c-bfm

A quick I2C BFM for I2C device testing and development

Language: SystemVerilog - Size: 7.81 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 1

ucsbieee/arcade

6502 Arcade Machine by UCSB IEEE

Language: JavaScript - Size: 6.57 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 5 - Forks: 2

midimaster21b/rtl-core-library

A set of common RTL cores that I've developed over time and organized into a FuseSoC library.

Size: 21.5 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

midimaster21b/three-wire-spi-ad

Analog Digital Three Wire SPI

Language: VHDL - Size: 26.4 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

midimaster21b/axis-bfm

A simple AXIS BFM

Language: SystemVerilog - Size: 11.7 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

midimaster21b/SHA-Module

A simple SHA-256 implementation in VHDL and Verilog, simulated using a basic UVM testbench.

Language: Verilog - Size: 64.5 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

librecores/docker-tools

Just a set of Dockerfiles and tools for FuseSoC

Language: Dockerfile - Size: 19.5 KB - Last synced at: 12 months ago - Pushed at: over 6 years ago - Stars: 6 - Forks: 5

euripedesrocha/tbpp

A simple test library for verilator

Language: C++ - Size: 128 KB - Last synced at: about 1 month ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0