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GitHub topics: veer

chipsalliance/Cores-VeeR-EH1

VeeR EH1 core

Language: SystemVerilog - Size: 17.6 MB - Last synced at: 14 days ago - Pushed at: almost 2 years ago - Stars: 870 - Forks: 227

chipsalliance/VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2

Language: Verilog - Size: 1.38 MB - Last synced at: 26 days ago - Pushed at: 5 months ago - Stars: 311 - Forks: 70

Related Keywords
fusesoc 2 veer 2 tools 1 swerv 1 western-digital 1 verilator 1 rtl 1 riscv32 1 riscv 1 risc-v 1 risc 1 processor 1 open-source-hardware 1 fpga 1 axi4 1 asic-design 1 ahb-lite 1