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GitHub topics: axi4-lite-interface

muhammadtalhasami/Axi4_lite_interface

This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .

Language: SystemVerilog - Size: 104 KB - Last synced at: 5 days ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 1

arhamhashmi01/Axi4-lite

This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

Language: SystemVerilog - Size: 390 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Ammar-Bin-Amir/AXI4

RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle

Language: Verilog - Size: 19.5 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

dpretet/meduram

Multi-port BRAM IP for ASIC and FPGA

Language: SystemVerilog - Size: 241 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 10 - Forks: 2

Related Keywords
axi4-lite-interface 4 axi4 3 axi4-lite 3 axi4-protocol 2 verilator 2 yosys 1 svut 1 ram 1 multi-port 1 iverilog 1 fusesoc 1 fpga 1 bram 1 block 1 asic 1 amba 1 verilog 1 rtl-design 1 handshaking-algorithm 1 bus-protocol 1 vivado-simulator 1 systemverilog 1 hardware-designs 1 vivado 1 system-verilog 1 axi4-lite-system-verilog 1