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GitHub topics: systemverilog-developer

chipsalliance/verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Language: C++ - Size: 12.7 MB - Last synced at: about 15 hours ago - Pushed at: about 15 hours ago - Stars: 1,554 - Forks: 238

xver/icecream_sv

IceCream for SystemVerilog: Never use $display and `uvm_info to debug SystemVerilog again.

Language: SystemVerilog - Size: 216 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

WajahatRiaz/AHB-Lite-Protocol-Verification

Attempt to develop a verification IP and plan for a bus functional model of ARM based AMBA 3 AHB-LITE Protocol. Implemented object oriented programming techniques in SysteVerilog.

Language: SystemVerilog - Size: 2.3 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 4 - Forks: 0