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GitHub / jakubcabal / uart-for-fpga
Simple UART controller for FPGA written in VHDL
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jakubcabal%2Fuart-for-fpga
Stars: 65
Forks: 23
Open Issues: 1
License: mit
Language: VHDL
Repo Size: 97.7 KB
Dependencies:
0
Created: almost 9 years ago
Updated: over 1 year ago
Last pushed: almost 3 years ago
Last synced: about 1 year ago
Topics: controller, cyc1000, fpga, ghdl, simulation, uart, uart-controller, uart-loopback, vhdl, wishbone, wishbone-bus
Files
No dependencies found