GitHub / jakubcabal / uart-for-fpga
Simple UART controller for FPGA written in VHDL
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Stars: 65
Forks: 23
Open issues: 1
License: mit
Language: VHDL
Size: 97.7 KB
Dependencies parsed at: Pending
Created at: almost 10 years ago
Updated at: over 2 years ago
Pushed at: almost 4 years ago
Last synced at: over 2 years ago
Topics: controller, cyc1000, fpga, ghdl, simulation, uart, uart-controller, uart-loopback, vhdl, wishbone, wishbone-bus
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