GitHub / jakubcabal / uart-for-fpga

Simple UART controller for FPGA written in VHDL

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PURL: pkg:github/jakubcabal/uart-for-fpga

Stars: 101
Forks: 30
Open issues: 1

License: mit
Language: VHDL
Size: 97.7 KB
Dependencies parsed at: Pending

Created at: about 10 years ago
Updated at: 10 days ago
Pushed at: about 4 years ago
Last synced at: 8 days ago

Topics: controller, cyc1000, fpga, ghdl, simulation, uart, uart-controller, uart-loopback, vhdl, wishbone, wishbone-bus

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