GitHub / stnolting / neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/stnolting%2Fneorv32-verilog
Stars: 89
Forks: 19
Open issues: 0
License: bsd-3-clause
Language: VHDL
Size: 318 KB
Dependencies parsed at: Pending
Created at: almost 3 years ago
Updated at: about 19 hours ago
Pushed at: about 19 hours ago
Last synced at: about 10 hours ago
Topics: asic, fpga, ghdl, icarus-verilog, neorv32, verilog
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