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GitHub / rschlaikjer / fpga-3-softcores

Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/rschlaikjer%2Ffpga-3-softcores

Stars: 4
Forks: 2
Open issues: 0

License: mit
Language: Verilog
Size: 10 MB
Dependencies parsed at: Pending

Created at: over 4 years ago
Updated at: almost 3 years ago
Pushed at: over 4 years ago
Last synced at: about 2 years ago

Topics: fpga, risc-v, softcore, wishbone

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