GitHub topics: cadence-virtuoso
RarityBrown/blog
Some ramblings about my major. 一些有关我的专业的碎碎念
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SKpro-glitch/Resume
Find my resume, encapsulating my most prominent projects and experiences relevant for an entry level Hardware Engineering role. - Soham Kapur
Size: 270 KB - Last synced at: 8 days ago - Pushed at: 8 days ago - Stars: 0 - Forks: 0
ryanhighlander/PLL
Partition Linux Loader - boot a linux kernel directly from a disk partition
Language: Assembly - Size: 23.4 KB - Last synced at: 21 days ago - Pushed at: 21 days ago - Stars: 0 - Forks: 0
arm-university/VLSI-Fundamentals-Education-Kit
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor
Language: HTML - Size: 201 MB - Last synced at: 29 days ago - Pushed at: 9 months ago - Stars: 232 - Forks: 56
joetho786/PyCadence
Python SDK to run simulation on cadence and automate process.
Language: Python - Size: 201 KB - Last synced at: 12 days ago - Pushed at: 8 months ago - Stars: 3 - Forks: 0
ranjith-dhananjaya/Cadence-lab-simulations
This repository contains the files (schematic, test bench, simulation results) from the course Mixed-Signal Design(undergrad)
Size: 1.22 MB - Last synced at: about 2 months ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0
rpm2003rpm/vagen
Generates verilogA testbench (stimulus and waveforms) for verification of analog IPs (VLSI design)
Language: Python - Size: 1.6 MB - Last synced at: 20 days ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 0
LijinWilson/CMOS-NAND-gate-2-input-NAND-gate
This repository contains the design, simulation, and performance evaluation of a CMOS NAND Gate using Cadence Virtuoso. The project highlights the design principles and operational characteristics of a fundamental digital logic gate implemented with CMOS technology.
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LijinWilson/CMOS-Inverter
This repository contains the design, simulation, and analysis of a CMOS Inverter using industry-standard tools like Cadence Virtuoso. The project focuses on understanding and optimizing the fundamental building block of digital circuits—the CMOS inverter.
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muhammadaldacher/Analog-Design-of-Asynchronous-SAR-ADC
This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.
Size: 46.1 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 140 - Forks: 18
EswarAdithya011/Mealy-Sequence-Detector-CMOS-90nm
This repository contains the design and implementation of a 4-bit Mealy Machine-based Overlapping Sequence Detector for detecting the sequence "1001" using 90nm CMOS technology and simulated in Cadence Virtuoso. The design employs SISO registers and master-negative edge-triggered D flip-flops within a Mealy machine architecture.
Size: 1.37 MB - Last synced at: 3 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0
martinnl/daisyLayoutAssist
Tool to create mapping between schematic and layout in Cadence Virtuoso to simplify layout.
Size: 42 KB - Last synced at: 2 months ago - Pushed at: over 6 years ago - Stars: 7 - Forks: 1
electronics-and-drives/SPAM
SKILL Package Manager
Size: 32.2 KB - Last synced at: 5 months ago - Pushed at: about 6 years ago - Stars: 9 - Forks: 2
mdmfernandes/smoc 📦
A stochastic circuit optimizer for Cadence Virtuoso, using the NSGA-II genetic algorithm.
Language: Python - Size: 1.14 MB - Last synced at: 22 days ago - Pushed at: over 3 years ago - Stars: 11 - Forks: 5
SalomeDevkule7/Carry-Select-Adder-8-bit
VLSI Physical Design
Size: 271 KB - Last synced at: 5 months ago - Pushed at: almost 7 years ago - Stars: 5 - Forks: 1
Yellowflash-070/4bit-RCA-180nm-Layout
Layout of 4bit Ripple Carry Adder formed using CMOS logic in gpdk180nm technology node done in Cadence Virtuoso with no DRC and LVS errors.
Size: 20.5 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 1 - Forks: 0
Yellowflash-070/4bitRCA180nm
Performance Analysis of a 4-bit Ripple Carry Adder (RCA) formed using Static CMOS, Transmission Gate, NMOS Pass Transistor Logic at gpdk 180nm Technology node.
Size: 4.05 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0
unihd-cag/skillbridge
A seamless python to Cadence Virtuoso Skill interface
Language: Python - Size: 944 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 159 - Forks: 34
SaiVarshit/Digital-circuit-Simulation-in-Cadence-Microwind-and-NGspice
A practical Introduction to simulation software's
Size: 2.26 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0
levinit/cds-git Fork of rbennell-gh/cdsgit_lfs
Cadence Virtuoso Git Integration written in SKILL++, forked from rbennell-gh/cdsgit_lfs, and the cdsgit_lsf is forked from https://github.com/cdsgit/cdsgit
Size: 1.42 MB - Last synced at: 7 days ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0
mdmfernandes/socad 📦
Connect Cadence Virtuoso to a Python client using sockets.
Language: Python - Size: 123 KB - Last synced at: 22 days ago - Pushed at: over 4 years ago - Stars: 15 - Forks: 9
cascode-labs/softworks
Software and documentation views in Cadence Virtuoso
Language: Python - Size: 2.27 MB - Last synced at: 29 days ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 0
AugustUnderground/vim-skill
SKILL / SKILL++ Syntax highlighting for vim
Language: Vim script - Size: 19.5 KB - Last synced at: about 2 months ago - Pushed at: over 3 years ago - Stars: 7 - Forks: 4
PriyankaGoradia/invertor
Designed and simulated an inverter in Cadence
Size: 1.26 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
afzalamu/single-stage-opamp-design-using-gpdk180-in-cadence
This repository contains a simple approach to design single stage operational amplifier using gpdk180 in Cadence Virtuoso.
Size: 50.8 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
unnir/CadenceSKILL-Python
Inter Process Communication (IPC) between Python and Cadence Virtuoso
Language: Python - Size: 68.4 KB - Last synced at: about 1 year ago - Pushed at: over 8 years ago - Stars: 71 - Forks: 17
ads930/4_bit_adder
This is a 4-bit pipelined carry-ripple adder. The design has been optimized for delay. To view the project, download the zip file and open the project in Cadence Virtuoso.
Size: 281 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 0
muhammadaldacher/Layout-Design-of-an-8x8-SRAM-array
The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static Noise Margin is obtained through Matlab scripts.
Language: MATLAB - Size: 6.05 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 41 - Forks: 6
rhovector/Cadence_Virtuoso_180nm_Projects
Schematic, Layout Design & Simulation in 180nm Technology
Size: 77.1 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 10 - Forks: 1
ColsonZhang/VerilogA-Wave-Generator
The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuction is to generate the specific waveforms according to your setting.And the setting is done in the python code (main.py), which will facilitate greatly the coding works.
Language: Python - Size: 183 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 32 - Forks: 9
muhammadaldacher/Analog-Design-of-Dynamic-Comparator
This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Power / (fs*2ENOB).
Size: 18.6 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 2
bishalpaudelofficial/Analog-IC-Design
Fundamental analog circuit designs to kick start and embark the journey in the world of IC design.
Size: 12.2 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 4 - Forks: 1
matthschw/eda-acronyms
Electronic Design Automation (EDA) Acronyms
Language: TeX - Size: 1.97 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0
matthschw/bondtools
Toolbox for creating a bonding diagram in Cadence Virtuoso
Language: HCL - Size: 304 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 1
matthschw/skill-sch2sym
Transform a Cadence Virtuoso Schematic in a Symbol
Size: 271 KB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
matthschw/sch2tikz
schematic to tikzpicture converter for Cadence Virtuoso
Language: TeX - Size: 117 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
shandilyaguy247/ECE3002_VLSI_System_Design
Contains all the necessary lab tasks (Cadence Virtuoso) for ECE3002 VLSI System Design (VIT).
Size: 4.15 MB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0
martinnl/daisy Fork of jjwikner/daisy
Framework to organize IC design projects.
Language: Emacs Lisp - Size: 7.63 MB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 7 - Forks: 0
matthschw/skill-JSON
Convert JSON from and to Cadence Skill
Size: 28.3 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 1
muhammadaldacher/Analog-Design-of-1.9-GHz-PLL-system
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
Language: MATLAB - Size: 33.9 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 31 - Forks: 8
MatteoOrlandini/Micro-Nano-Electronic-Exam
Design of a sixth order elliptical low pass filter in cascade design with Switched Capacitor second stages order of type biquad
Language: MATLAB - Size: 4.08 MB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 1
cascode-labs/SKILL Fork of ananthchellappa/SKILL
A SKILL Library for Cadence Virtuoso
Size: 645 KB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 0
NARDEEPsinghSHEKHAWAT/VERILOG-VLSI-CODES
Some codes I have implemented during my 10 day Training under VLSI DOMAIN
Size: 1000 Bytes - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0
IFTE-EDA/SKILLdoc-ng
Documentation generator for Cadence Virtuoso SKILL (SKILL++) packages.
Language: Lua - Size: 199 KB - Last synced at: over 1 year ago - Pushed at: about 10 years ago - Stars: 2 - Forks: 0
zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
Language: Verilog - Size: 1.51 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 62 - Forks: 26
muhammadaldacher/RF-design-of-1.9-GHz-Rx-frontend
This project shows the design process of the main blocks of a typical RX frontend system.
Size: 26.3 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 17 - Forks: 3
muhammadaldacher/RF-design-of-2.4-GHz-LNA
This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.
Size: 668 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 5 - Forks: 3
Supriya-M-Ravichandran/Single-Stage-Amplifier-Design
Design of Differential Input Single Ended Output Single Stage Amplifier
Size: 14.6 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0
akdimitri/RRAM_COMPILER
This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of Dimitris Antoniadis (PG Taught Student) at Imperial College London
Language: HTML - Size: 12.3 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 27 - Forks: 6
muhammadaldacher/Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC
This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
Language: MATLAB - Size: 8.11 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 11 - Forks: 7
ranjith-dhananjaya/CMOS-OTA-design-using-Cadence-45nm-process-technology
A 2 stage CMOS OTA with Differential amplifier with active load as the first stage followed by Common Source stage using Cadence
Size: 2.91 MB - Last synced at: about 2 months ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 2
muhammadaldacher/Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
Size: 11.4 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 10 - Forks: 4
muhammadaldacher/Modeling-of-4-bit-Flash-ADC-and-4-bit-DAC
This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 4-bit ADC based on the flash architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
Language: MATLAB - Size: 3.67 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 6 - Forks: 3
muhammadaldacher/Analog-design-of-4-bit-current-steering-DACs
This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using high-swing cascode current mirror structures for the current source arrays.
Size: 12.2 MB - Last synced at: about 2 years ago - Pushed at: almost 6 years ago - Stars: 6 - Forks: 2
electronics-and-drives/SKILLFFI
Foreign Function Interface for Cadence SKILL
Language: C - Size: 33.2 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 4 - Forks: 0
electronics-and-drives/SAM
E&D Skill Application Manager (SAM)
Language: Shell - Size: 61.5 KB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0
matthschw/ed-spectre-lib
Models for Simulation in Cadence Spectre
Size: 167 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 1
exarchou/FPGA-Cadence-Virtuoso
Designing of a switch box for FPGA circuits in Cadence Virtuoso software. Circuit analysis and implementation of the physical layout.
Size: 1.22 MB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 1
Nived151/FET-DigitalLib
A Collection of Digital Library of both Schematic & Layout using 70nm FET
Language: Tcl - Size: 617 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 2
cdsdm/cdsdm
Cadence Virtuoso Design Management System
Size: 39.1 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 23 - Forks: 8
Nived151/CMOS-DigitalLib
Collection of Digital Library in cadence of 45nm
Size: 948 KB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 2
electronics-and-drives/ed-spectre-lib Fork of matthschw/ed-spectre-lib
Models for Simulation in Cadence Spectre
Size: 153 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
matthschw/cds-bindkeys
Cadence Virtuoso Bindkeys
Language: TeX - Size: 965 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 1
electronics-and-drives/libvc
Virtuoso Communication Interface shared library.
Language: C++ - Size: 4.88 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 2 - Forks: 0
AK1194/Time-Interleaved-SAR-ADC-Analog-VLSI-Design-Cadence-Virtuoso
This repository is about design and implementation of a time interleaved SAR ADC in Cadence Virtuoso. In this project all the blocks of the ADC is customised and implemented from transistor level itself and no ideal block is used from the libraries of virtuoso.
Size: 0 Bytes - Last synced at: over 1 year ago - Pushed at: about 8 years ago - Stars: 0 - Forks: 2
