GitHub topics: pll

Repositories

PU2REO/Si5351ArduinoLite

Library for the Si5351A (10 MSOP - 3 Clocks Only) clock generator IC in the Arduino environment , based on NT7S library.

Language: C++ - Size: 209 KB - Last synced at: about 3 hours ago - Pushed at: about 4 hours ago - Stars: 5 - Forks: 2

afzalamu/Design-of-Phase-locked-loop-for-2.4-GHz-frequency-in-180nm-Technology

Design of Phase locked loop for 2.4 GHz frequency in 180nm Technology

Size: 210 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

SpiderBlocker/TSA5511_PLL_Controller_Arduino

TSA5511 PLL Controller for Arduino

Language: C++ - Size: 410 KB - Last synced at: 5 days ago - Pushed at: 5 days ago - Stars: 2 - Forks: 0

Parhamdada/PLL_survey

A repository of the recently published PLLs performance.

Language: Python - Size: 197 KB - Last synced at: 7 days ago - Pushed at: 7 days ago - Stars: 0 - Forks: 0

super1207/FOC

sensorless fixed point foc use smo and pll in stm32

Language: C - Size: 10.7 KB - Last synced at: 17 days ago - Pushed at: 17 days ago - Stars: 27 - Forks: 9

long27032002/GPS_GNSS_Disciplined_Oscillator

GPS disciplined oscillator project aims to create a clock source device with eight 10MHz outputs adjust by the 1PPS signal from the GGPS/GNSS module and PLL circuit.

Language: C - Size: 27.5 MB - Last synced at: 26 days ago - Pushed at: 26 days ago - Stars: 3 - Forks: 0

ryanhighlander/PLL

Partition Linux Loader - boot a linux kernel directly from a disk partition

Language: Assembly - Size: 23.4 KB - Last synced at: 27 days ago - Pushed at: 27 days ago - Stars: 0 - Forks: 0

Atrimax18/ADF4368_Register

ADF4368 register control application

Language: C# - Size: 73.2 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

junon10/tsa5511

tsa5511/12 fm pll

Language: Assembly - Size: 65.4 KB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

junon10/saa1057-stereo-pll

SAA1057 Stereo PLL Controller

Language: Assembly - Size: 110 KB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

junon10/saa1057

SAA1057 PLL Controller Arduino Library

Language: C++ - Size: 39.1 KB - Last synced at: 22 days ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 2

junon10/mc145158

MC145158 PLL Arduino Controller Library

Language: C++ - Size: 651 KB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

kromych/pico-pll-config

Generating PLL configuration parameters

Language: Rust - Size: 9.77 KB - Last synced at: 1 day ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

FPGAwars/icePLL

PLL collection for IceStudio

Language: JavaScript - Size: 154 KB - Last synced at: 20 days ago - Pushed at: 3 months ago - Stars: 2 - Forks: 2

ranjith-dhananjaya/20GHz-integer-N-PLL-in-65nm-CMOS-process

Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using 𝑉𝐷𝐷 of 1.2V in Cadence 65nm CMOS process

Size: 3.71 MB - Last synced at: about 2 months ago - Pushed at: almost 3 years ago - Stars: 4 - Forks: 2

maciejskorski/enhanced-pll-trng

Data and code to design and evaluate the PLL-based true random number generator according to the paper "Enhancing Quality and Security of the PLL-TRNG" (published and awarded at TCHES 2023).

Language: Jupyter Notebook - Size: 290 MB - Last synced at: 15 days ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0

8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

Size: 25.3 MB - Last synced at: 5 months ago - Pushed at: over 3 years ago - Stars: 108 - Forks: 41

ZipCPU/dpll

A collection of phase locked loop (PLL) related projects

Language: Verilog - Size: 690 KB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 99 - Forks: 26

italspazio-com/pll-to-cpp

Grafico PLL animato in C++

Language: C++ - Size: 16.1 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

vk2diy/23cm Fork of pe1jpd/23cm

23cm NBFM transceiver

Language: C - Size: 8.56 MB - Last synced at: 7 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

zhinst/blogs

Support files for blog posts of Zurich Instruments

Language: Jupyter Notebook - Size: 1.66 MB - Last synced at: 2 days ago - Pushed at: 9 months ago - Stars: 9 - Forks: 11

angrram/3ph_pll

Three phase (3PH) DSOGI Phase Lock Loop (PLL)

Language: HTML - Size: 25.4 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0

pavelmc/Si5351mcu

Arduino Si5351 library tuned for size and click free.

Language: C++ - Size: 85.9 KB - Last synced at: 9 months ago - Pushed at: about 3 years ago - Stars: 60 - Forks: 25

sv1onw/Si5351_OLED_DFS_CW

Modified version of Si5351_OLED_DFS for simple CW TX use or DC receiver.

Language: C++ - Size: 2.12 MB - Last synced at: 21 days ago - Pushed at: about 6 years ago - Stars: 4 - Forks: 1

sv1onw/Si5351_OLED_DFS

Very minimalistic 20meter transceiver Digital Frequency Synthesizer with 0.96 or 1.3 inch 128x64 OLED Display for Ham-radio use

Language: C++ - Size: 3.65 MB - Last synced at: 21 days ago - Pushed at: about 6 years ago - Stars: 5 - Forks: 1

iDoka/eda-scripts

Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)

Language: Shell - Size: 220 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 25 - Forks: 2

TU-Darmstadt-APQ/MTS-module_80MHz_200MHz

Alternative version of the MTS module (https://github.com/TU-Darmstadt-APQ/MTS_module) for 80 MHz and 200 MHz AOMs.

Size: 20.1 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

yonicon/DynamicModeAFM

A Simulink Model of Dynamic Mode AFM

Language: MATLAB - Size: 126 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

charkster/adc_block_ram_spi_top

Xilinx Artix-7 FPGA design using block ram, XADC and a SPI slave (SCARF). The block ram is dual port and can be written by either SPI or XADC samples, and only read by SPI.

Language: SystemVerilog - Size: 212 KB - Last synced at: about 2 months ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 1

frifle/adventskalender

Ein alternativer Elektronik-Adventskalender für das Jahr 2023

Language: HTML - Size: 6.21 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 0

ke0ff/ICOM_UXFF_RevT

Source and support for the UXFFront module revision-T (TX/RX) for the ICOM IC-900/IC-901 UX radio modules

Size: 241 KB - Last synced at: about 2 months ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

oliviercotte/All-digital-modulator

All digital lowpas delta-sigma modulator (+digital up-converter) tune to fmax = 9 MHz

Language: HTML - Size: 128 MB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 3

smonteillet/pll-trainer

Train your PLL skills on Rubik's cube with this groovy script

Language: Groovy - Size: 179 KB - Last synced at: over 1 year ago - Pushed at: about 7 years ago - Stars: 2 - Forks: 0

abranhe/react-pll

<Pll/> React Programming Language Logo Component.

Language: JavaScript - Size: 72.3 KB - Last synced at: 23 days ago - Pushed at: 8 months ago - Stars: 9 - Forks: 0

americodias/sca_pll

PLL Simulator in SystemC-AMS

Language: C++ - Size: 1.14 MB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 5 - Forks: 1

ilyajob05/verilog_modules

verilog modules

Language: Verilog - Size: 27.3 KB - Last synced at: almost 2 years ago - Pushed at: almost 5 years ago - Stars: 8 - Forks: 2

Eyantra698Sumanto/VSDOpen_PLL_Tutorial

This repo contains documentation of the "VSD Open On-Chip Clock Multiplier (PLL) on OSU180" tutorial.

Size: 88.9 KB - Last synced at: about 2 months ago - Pushed at: almost 3 years ago - Stars: 4 - Forks: 1

Enanter/ADPLL

All Digital Phase-Locked Loop

Language: Tcl - Size: 60.7 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

muhammadaldacher/Analog-Design-of-1.9-GHz-PLL-system

This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.

Language: MATLAB - Size: 33.9 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 31 - Forks: 8

XiangYyang/SOGI-PLL

Single-Phase PLL / Second-Order Generalized Integrators Phase Lock Loop

Language: C++ - Size: 12.7 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

fahr-khadija/PLL-IC-Design

Design and generate the GDSII file for an 8x PLL Clock Multiplier IP with open source PDK & tools

Size: 38.1 KB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

cracked-machine/GuitarPLLSynthEffect

Guitar triggered PLL Synth effect

Size: 1.65 MB - Last synced at: 9 months ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

afch/DDS-AD9915-Arduino-Shield

Firmware (Sketch) for Arduino MEGA DDS (Direct Digital Synthesis) Analog Devices AD9915 Arduino Shield by GRA & AFCH

Size: 1.95 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

NightIsDark/RFFC

RFFC2071 C8051F330

Language: C - Size: 195 KB - Last synced at: almost 2 years ago - Pushed at: almost 7 years ago - Stars: 10 - Forks: 8

sjain-stanford/SCM-PLL

Self consistent model based filter design for 3-phase PLLs.

Language: Makefile - Size: 49.7 MB - Last synced at: about 1 month ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

microchip-pic-avr-examples/avr128db48-high-freq-clk-generation-using-pll-and-oschf-mplab

This code example demonstrates usage of AVR128DB48 microcontroller to generate 48MHz clock signal using PLL and OSCHF. In this code example, use of Timer/Counter type D (TCD) peripheral to realize peripheral clock frequency of 48MHz is demonstrated.

Language: C - Size: 668 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

r4d10n/iCEstick-hacks

iCEstick iCE40-HX1K FPGA hacks ~ iCEfm FM Transmitter

Language: Verilog - Size: 2.93 KB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 16 - Forks: 1

muhammadaldacher/Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS

This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.

Size: 11.4 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 10 - Forks: 4

heyshakya/vsd_pll

8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

Size: 8.78 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 3 - Forks: 1

Micwsr/rubik_solver

A 3x3 rubik's cube solver made with python using the CFOP method.

Language: Python - Size: 563 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

microchip-pic-avr-solutions/mchv3-dspic33ck256mp508-an1206

Sensorless FOC (PLL estimator) of AC induction motor with field weakening

Language: C - Size: 9.5 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 2

hansonTang01/PLL

Implementation of Pruned landmark algorithm

Language: Python - Size: 11.8 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

parasgidd/avsdpll_3v3

This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.

Language: SourcePawn - Size: 4.52 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 12 - Forks: 5

sascha-kirch/Bit_Error_Tester

This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.

Language: Verilog - Size: 883 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 6 - Forks: 0

Related Keywords

pll 65 fpga 8 matlab 5 analog-design 4 asic 4 spi 4 fm-transmitter 4 pll-controller 4 verilog 4 transceiver 4 ham-radio 4 python 3 vco 3 fm 3 digital 3 mikroc 3 transmitter 3 fm-synthesizer 3 magic 3 clock-multiplier 3 cadence-virtuoso 3 c 3 cfop 3 arduino-library 3 si5351a 3 arduino 3 smo 2 radio 2 adf4351 2 rf 2 analog 2 charge-pump 2 design 2 analog-circuit 2 ic 2 rtl2gds 2 oll 2 f2l 2 simulink 2 display 2 frequency 2 oled 2 synthesizer 2 xilinx 2 oscillator 2 simulink-model 2 frequency-divider 2 clock-generator 2 fm-radio 2 keil-uvision 2 rubiks-cube-scrambler 2 rubiks-cube 2 foc 2 10mhz 2 i2c 2 gpio 2 bldc 2 mikroc-pro-for-pic 2 control-systems 2 vfo 2 tsa5511 2 mixed-signal 2 sogi-pll 2 logic-programming 1 veriloga 1 discrete-systems 1 power-electronics 1 prolog 1 internal-high-frequency-oscillator 1 audio 1 fx 1 self-consistency 1 guitar 1 stompbox 1 swing-gui 1 mikrosdk 1 synth 1 ad9914 1 microchip-pic 1 ad9915 1 direct-digital-synthesis 1 generator 1 low-noise 1 tranceiver 1 rffc2071 1 filter-design 1 mathematical-modelling 1 tec 1 java 1 scramble 1 haskell 1 programming-languages-logos 1 react 1 systemc 1 systemc-ams 1 7-segment 1 memory 1 nexys-4-spartan-3e 1 nexys4 1 nexys4-board 1