Ecosyste.ms: Repos
An open API service providing repository metadata for many open source software ecosystems.
GitHub topics: pll
FPGAwars/icePLL
PLL collection for IceStudio
Language: JavaScript - Size: 190 KB - Last synced at: 14 days ago - Pushed at: 15 days ago - Stars: 2 - Forks: 2
super1207/FOC
sensorless fixed point foc use smo and pll in stm32
Language: C - Size: 10.7 KB - Last synced at: about 2 months ago - Pushed at: 8 months ago - Stars: 12 - Forks: 4
zhinst/blogs
Support files for blog posts of Zurich Instruments
Language: Jupyter Notebook - Size: 1.65 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 7 - Forks: 11
TU-Darmstadt-APQ/MTS-module_80MHz_200MHz
Alternative version of the MTS module (https://github.com/TU-Darmstadt-APQ/MTS_module) for 80 MHz and 200 MHz AOMs.
Size: 20.1 MB - Last synced at: 3 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0
ZipCPU/dpll
A collection of phase locked loop (PLL) related projects
Language: Verilog - Size: 690 KB - Last synced at: 2 months ago - Pushed at: 5 months ago - Stars: 87 - Forks: 25
angrram/3ph_pll
Three phase (3PH) DSOGI Phase Lock Loop (PLL)
Size: 1.72 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0
yonicon/DynamicModeAFM
A Simulink Model of Dynamic Mode AFM
Language: MATLAB - Size: 126 KB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0
pavelmc/Si5351mcu
Arduino Si5351 library tuned for size and click free.
Language: C++ - Size: 85.9 KB - Last synced at: 2 months ago - Pushed at: about 2 years ago - Stars: 57 - Forks: 25
PU2REO/Si5351ArduinoLite
Library for the Si5351A (10 MSOP - 3 Clocks Only) clock generator IC in the Arduino environment , based on NT7S library.
Language: C++ - Size: 103 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0
frifle/adventskalender
Ein alternativer Elektronik-Adventskalender für das Jahr 2023
Language: HTML - Size: 6.21 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 3 - Forks: 0
iDoka/eda-scripts
Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
Language: Shell - Size: 215 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 20 - Forks: 1
oliviercotte/All-digital-modulator
All digital lowpas delta-sigma modulator (+digital up-converter) tune to fmax = 9 MHz
Language: HTML - Size: 128 MB - Last synced at: 10 months ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 3
smonteillet/pll-trainer
Train your PLL skills on Rubik's cube with this groovy script
Language: Groovy - Size: 179 KB - Last synced at: 10 months ago - Pushed at: about 6 years ago - Stars: 2 - Forks: 0
maciejskorski/enhanced-pll-trng
Data and code to design and evaluate the PLL-based true random number generator according to the paper "Enhancing Quality and Security of the PLL-TRNG" (published at TCHES 2023).
Language: Jupyter Notebook - Size: 290 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0
abranhe/react-pll
<Pll/> React Programming Language Logo Component.
Language: JavaScript - Size: 70.3 KB - Last synced at: 8 days ago - Pushed at: over 4 years ago - Stars: 9 - Forks: 0
americodias/sca_pll
PLL Simulator in SystemC-AMS
Language: C++ - Size: 1.14 MB - Last synced at: 8 months ago - Pushed at: about 1 year ago - Stars: 5 - Forks: 1
ilyajob05/verilog_modules
verilog modules
Language: Verilog - Size: 27.3 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 8 - Forks: 2
Enanter/ADPLL
All Digital Phase-Locked Loop
Language: Tcl - Size: 60.7 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
muhammadaldacher/Analog-Design-of-1.9-GHz-PLL-system
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
Language: MATLAB - Size: 33.9 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 31 - Forks: 8
XiangYyang/SOGI-PLL
Single-Phase PLL / Second-Order Generalized Integrators Phase Lock Loop
Language: C++ - Size: 12.7 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0
fahr-khadija/PLL-IC-Design
Design and generate the GDSII file for an 8x PLL Clock Multiplier IP with open source PDK & tools
Size: 38.1 KB - Last synced at: 11 months ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0
afch/DDS-AD9915-Arduino-Shield
Firmware (Sketch) for Arduino MEGA DDS (Direct Digital Synthesis) Analog Devices AD9915 Arduino Shield by GRA & AFCH
Size: 1.95 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
NightIsDark/RFFC
RFFC2071 C8051F330
Language: C - Size: 195 KB - Last synced at: about 1 year ago - Pushed at: almost 6 years ago - Stars: 10 - Forks: 8
sjain-stanford/SCM-PLL
Self consistent model based filter design for 3-phase PLLs.
Language: Makefile - Size: 49.7 MB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0
microchip-pic-avr-examples/avr128db48-high-freq-clk-generation-using-pll-and-oschf-mplab
This code example demonstrates usage of AVR128DB48 microcontroller to generate 48MHz clock signal using PLL and OSCHF. In this code example, use of Timer/Counter type D (TCD) peripheral to realize peripheral clock frequency of 48MHz is demonstrated.
Language: C - Size: 668 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
r4d10n/iCEstick-hacks
iCEstick iCE40-HX1K FPGA hacks ~ iCEfm FM Transmitter
Language: Verilog - Size: 2.93 KB - Last synced at: over 1 year ago - Pushed at: almost 7 years ago - Stars: 16 - Forks: 1
lakshmi-sathi/avsdpll_1v8
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
Size: 25.3 MB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 95 - Forks: 42
muhammadaldacher/Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
Size: 11.4 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 10 - Forks: 4
heyshakya/vsd_pll
8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
Size: 8.78 MB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 1
Micwsr/rubik_solver
A 3x3 rubik's cube solver made with python using the CFOP method.
Language: Python - Size: 563 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
microchip-pic-avr-solutions/mchv3-dspic33ck256mp508-an1206
Sensorless FOC (PLL estimator) of AC induction motor with field weakening
Language: C - Size: 9.5 MB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 2
hansonTang01/PLL
Implementation of Pruned landmark algorithm
Language: Python - Size: 11.8 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0
parasgidd/avsdpll_3v3
This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.
Language: SourcePawn - Size: 4.52 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 12 - Forks: 5
sascha-kirch/Bit_Error_Tester
This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.
Language: Verilog - Size: 883 KB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 6 - Forks: 0
sv1onw/Si5351_OLED_DFS_CW
Modified version of Si5351_OLED_DFS for simple CW TX use or DC receiver.
Language: C++ - Size: 2.12 MB - Last synced at: over 1 year ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 0
electronicayciencia/pll_4046
Digital Frequency Synthesizer with PIC16F88 and CD4046.
Language: AGS Script - Size: 11.9 MB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 1
manish257/Vending-Machine-on-Keil-using-C-for-Tiva-C-Implementation
Language: Assembly - Size: 39.1 KB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
infini8-13/riscv-ms-soc
A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier
Language: Verilog - Size: 84 KB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0
Eyantra698Sumanto/VSDOpen_PLL_Tutorial
This repo contains documentation of the "VSD Open On-Chip Clock Multiplier (PLL) on OSU180" tutorial.
Size: 88.9 KB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 4 - Forks: 1
merledu/jigsaw
A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).
Language: Scala - Size: 128 KB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 2 - Forks: 5
Codemonkey1973/adf435xcfg
Command line tool to allow control of the Analog Devices ADF435x devices
Language: C - Size: 354 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
saiakarsh193/PyCube-Solver
Rubik's cube solver using CFOP
Language: Python - Size: 152 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
ke0ff/GPSDO-II
Ublox GPS carrier and GPSDO
Language: C - Size: 228 KB - Last synced at: almost 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 1
charkster/adc_block_ram_spi_top
Xilinx Artix-7 FPGA design using block ram, XADC and a SPI slave (SCARF). The block ram is dual port and can be written by either SPI or XADC samples, and only read by SPI.
Language: SystemVerilog - Size: 212 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
sh123/MC145192-arduino
MC145192 PLL synthesizer control library for Arduino
Language: C++ - Size: 6.84 KB - Last synced at: about 1 year ago - Pushed at: over 6 years ago - Stars: 4 - Forks: 2
ke0ff/ICOM_UXFF_RevT
Source and support for the UXFFront module revision-T (TX/RX) for the ICOM IC-900/IC-901 UX radio modules
Size: 241 KB - Last synced at: almost 1 year ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0
sravi1210/Programming-Languages-Lab-2020
Programming Languages Lab - IITG'2020
Language: Java - Size: 18.5 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0
sv1onw/Si5351_OLED_DFS
Very minimalistic 20meter transceiver Digital Frequency Synthesizer with 0.96 or 1.3 inch 128x64 OLED Display for Ham-radio use
Language: C++ - Size: 3.65 MB - Last synced at: over 1 year ago - Pushed at: about 5 years ago - Stars: 4 - Forks: 0
lmartorella/lm7001_si470_bridge
LM7001 to Si4703 FM tuner bridge
Language: Makefile - Size: 451 KB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0
Yongxiang-Guo/ADF4351_PLL
Using ADF4351/PLL to get the frequency you want by STM32F103 !
Language: C - Size: 1.17 MB - Last synced at: about 1 year ago - Pushed at: almost 5 years ago - Stars: 3 - Forks: 2
MikroElektronika/PLL_click
Library for ICS501.
Language: C - Size: 366 KB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0