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GitHub / ilyajob05 / verilog_modules
verilog modules
JSON API: https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ilyajob05%2Fverilog_modules
Stars: 8
Forks: 2
Open Issues: 0
License: mit
Language: Verilog
Repo Size: 27.3 KB
Dependencies: pending
Created: over 6 years ago
Updated: about 1 year ago
Last pushed: about 4 years ago
Last synced: almost 1 year ago
Topics: 7-segment, fpga, i2c, memory, nexys-4-spartan-3e, nexys4, nexys4-board, pll, rmii, spi, synchronization, timer, uart, usart, verilog, xilinx, xilinx-fpga