GitHub / ilyajob05 / verilog_modules

verilog modules

JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ilyajob05%2Fverilog_modules
PURL: pkg:github/ilyajob05/verilog_modules

Stars: 8
Forks: 2
Open issues: 0

License: mit
Language: Verilog
Size: 27.3 KB
Dependencies parsed at: Pending

Created at: about 8 years ago
Updated at: over 2 years ago
Pushed at: over 5 years ago
Last synced at: over 2 years ago

Topics: 7-segment, fpga, i2c, memory, nexys-4-spartan-3e, nexys4, nexys4-board, pll, rmii, spi, synchronization, timer, uart, usart, verilog, xilinx, xilinx-fpga

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