GitHub / sascha-kirch / Bit_Error_Tester
This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.
JSON API: http://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/sascha-kirch%2FBit_Error_Tester
Stars: 6
Forks: 0
Open issues: 0
License: mit
Language: Verilog
Size: 883 KB
Dependencies parsed at: Pending
Created at: about 4 years ago
Updated at: over 2 years ago
Pushed at: almost 3 years ago
Last synced at: about 2 years ago
Topics: bit-error-rate, clock-generator, fpga, pll, prbs-generator, verilog