GitHub topics: veriloga
RarityBrown/blog
Some ramblings about my major. 一些有关我的专业的碎碎念
Size: 797 KB - Last synced at: 2 days ago - Pushed at: 2 days ago - Stars: 2 - Forks: 0
rpm2003rpm/vagen
Generates verilogA testbench (stimulus and waveforms) for verification of analog IPs (VLSI design)
Language: Python - Size: 1.6 MB - Last synced at: 21 days ago - Pushed at: about 2 months ago - Stars: 1 - Forks: 0
Joschua-Conrad/Transient-Simulation-of-Dynamic-Comparator-Noise
Verilog-A test block for estimating noise and offset of a dynamic comparator in a transient simulation. Uses the Confidence-Boosting concept published at NEWCAS 2024.
Language: Verilog - Size: 1.96 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0
ax0080/Digital-Loop-Filter
Digital Loop Filter Realization
Language: Verilog - Size: 25.4 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0
nikacvet/vscode-verilogA
Language support in Visual Studio Code for VerilogA
Language: TypeScript - Size: 1020 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0
ColsonZhang/VerilogA-Wave-Generator
The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuction is to generate the specific waveforms according to your setting.And the setting is done in the python code (main.py), which will facilitate greatly the coding works.
Language: Python - Size: 183 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 32 - Forks: 9
akashlevy/WP-RRAM-SPICE-Model
A well-posed RRAM SPICE model implemented in Verilog-A, based on Stanford/ASU filamentary model, using code developed at UC Berkeley
Size: 1.95 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 2
muhammadaldacher/Analog-Design-of-1.9-GHz-PLL-system
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
Language: MATLAB - Size: 33.9 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 31 - Forks: 8
muhammadaldacher/Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC
This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 10-bit ADC based on 1-bit per stage pipelined architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
Language: MATLAB - Size: 8.11 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 11 - Forks: 7
muhammadaldacher/Modeling-of-4-bit-Flash-ADC-and-4-bit-DAC
This project shows how to model a 4-bit flash ADC and a 4-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, vccs to construct the 4-bit ADC based on the flash architecture. Models are built in Cadence using ideal components & VerilogA blocks, & Analysis is done on Matlab.
Language: MATLAB - Size: 3.67 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 6 - Forks: 3