GitHub / Joschua-Conrad / Transient-Simulation-of-Dynamic-Comparator-Noise
Verilog-A test block for estimating noise and offset of a dynamic comparator in a transient simulation. Uses the Confidence-Boosting concept published at NEWCAS 2024.
Stars: 0
Forks: 0
Open issues: 0
License: other
Language: Verilog
Size: 1.96 MB
Dependencies parsed at: Pending
Created at: about 1 year ago
Updated at: 12 months ago
Pushed at: 12 months ago
Last synced at: 12 months ago
Topics: analog, circuit, comparator, ieee, mixed-signal, noise, noise-estimation, simulation, transient, veriloga